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Each halfword of the result is the low-order 16 bits of the product of the corresponding halfwords of arg1 and arg2 added to the corresponding halfword of arg3.
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arg1 |
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vector unsigned short |
vector unsigned short |
vector unsigned short |
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vector signed short |
vector unsigned short |
vector signed short |
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vector signed short |
vector signed short |
vector unsigned short |
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vector signed short |
vector signed short |
vector signed short |
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