# Model-Specific Registers ## Topics ### Constants [`var HV_MSR_IA32_ARCH_CAPABILITIES: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_ARCH_CAPABILITIES) The value that represents the Model-Specific Register (MSR) that you use to enumerate processor capabilities. [`var HV_MSR_IA32_A_PMC0: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_A_PMC0) The value that represents support for address performance-counter register 0. [`var HV_MSR_IA32_A_PMC7: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_A_PMC7) The value that represents support for address performance-counter register 7. [`var HV_MSR_IA32_CSTAR: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_CSTAR) The value that represents the address of IA-32e Mode System Call Target Address. [`var HV_MSR_IA32_DEBUGCTL: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_DEBUGCTL) The value that represents the address of the Debug Control Register. [`var HV_MSR_IA32_EFER: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_EFER) The value that represents the address of the Entended Feature Enable Register (EFER). [`var HV_MSR_IA32_FIXED_CTR0: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_FIXED_CTR0) The value that represents the address of Fixed-Function Performance Counter Register 0. [`var HV_MSR_IA32_FIXED_CTR1: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_FIXED_CTR1) The value that represents the address of Fixed-Function Performance Counter Register 1. [`var HV_MSR_IA32_FIXED_CTR2: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_FIXED_CTR2) The value that represents the address of Fixed-Function Performance Counter Register 2. [`var HV_MSR_IA32_FIXED_CTR3: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_FIXED_CTR3) The value that represents the address of Fixed-Function Performance Counter Register 3. [`var HV_MSR_IA32_FIXED_CTR_CTRL: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_FIXED_CTR_CTRL) The value that represents the address of the Fixed-Function Counter Control Register. [`var HV_MSR_IA32_FLUSH_CMD: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_FLUSH_CMD) The value that represents the address of the Flush Command Register. [`var HV_MSR_IA32_FMASK: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_FMASK) The value that represents the address of the System Call Flag Mask (FMASK) Register. [`var HV_MSR_IA32_FS_BASE: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_FS_BASE) The value that represents the address of the map for the base address of the FS segment register. [`var HV_MSR_IA32_GS_BASE: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_GS_BASE) The value that represents the address of the map for the base address of the GS segment register. [`var HV_MSR_IA32_KERNEL_GS_BASE: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_KERNEL_GS_BASE) The value that represents the address swap target for the base address of the GS segment register. [`var HV_MSR_IA32_LSTAR: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_LSTAR) The value that represents the address of the IA-32e Mode System Call Target Address. [`var HV_MSR_IA32_PERFEVNTSEL0: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_PERFEVNTSEL0) The value that represents the address of Performance Event Select Counter 0. [`var HV_MSR_IA32_PERFEVNTSEL7: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_PERFEVNTSEL7) The value that represents the address of Performance Event Select Counter 7. [`var HV_MSR_IA32_PERF_GLOBAL_CTRL: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_PERF_GLOBAL_CTRL) The value that represents the address of the Global Performance Counter Control Register. [`var HV_MSR_IA32_PERF_GLOBAL_INUSE: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_PERF_GLOBAL_INUSE) The value that represents the address of the register that indicates whether the core performance monitor interface is in use. [`var HV_MSR_IA32_PERF_GLOBAL_STATUS: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_PERF_GLOBAL_STATUS) The value that represents the address of the Global Performance Status Register. [`var HV_MSR_IA32_PERF_GLOBAL_STATUS_RESET: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_PERF_GLOBAL_STATUS_RESET) The value that represents the address of the Global Performance Counter Overflow Reset Control Register. [`var HV_MSR_IA32_PERF_GLOBAL_STATUS_SET: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_PERF_GLOBAL_STATUS_SET) The value that represents the address of the Global Performance Counter Overflow Set Control Register. [`var HV_MSR_IA32_PMC0: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_PMC0) The value that represents the address of Performance Counter Register 0. [`var HV_MSR_IA32_PMC7: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_PMC7) The value that represents the address of Performance Counter Register 7. [`var HV_MSR_IA32_PRED_CMD: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_PRED_CMD) The value that represents the address of the Prediction Command Register. [`var HV_MSR_IA32_SPEC_CTRL: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_SPEC_CTRL) The value that represents the address of Speculation Control Register. [`var HV_MSR_IA32_STAR: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_STAR) The value that represents the address of the System Call Target Address Register. [`var HV_MSR_IA32_SYSENTER_CS: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_SYSENTER_CS) The value that represents the address of the CS Register target for Current Privilege Level (CPL) 0 code. [`var HV_MSR_IA32_SYSENTER_EIP: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_SYSENTER_EIP) The value that represents the address of the Extended Instruction Pointer (EIP) Register target for Current Privilege Level (CPL) 0 code. [`var HV_MSR_IA32_SYSENTER_ESP: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_SYSENTER_ESP) The value that represents the address of the Extended Stack Pointer (ESP) Register target for Current Privilege Level (CPL) 0 code. [`var HV_MSR_IA32_TSC: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_TSC) The value that represents the address of the Time-Stamp Counter Register. [`var HV_MSR_IA32_TSC_AUX: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_TSC_AUX) The value that represents the address of the Auxiliary Time-Stamp Counter Register. [`var HV_MSR_IA32_XSS: UInt32`](/documentation/Hypervisor/HV_MSR_IA32_XSS) The value that represents the address of the Extended Supervisors State Mask (XSS) Register. [`var HV_MSR_LASTBRANCH_0_FROM_IP: UInt32`](/documentation/Hypervisor/HV_MSR_LASTBRANCH_0_FROM_IP) The value that represents the address of the Last Branch Record 0 from Instruction Pointer (IP) register. [`var HV_MSR_LASTBRANCH_0_TO_IP: UInt32`](/documentation/Hypervisor/HV_MSR_LASTBRANCH_0_TO_IP) The value that represents the address of the Last Branch Record 0 to Instruction Pointer (IP) register. [`var HV_MSR_LASTBRANCH_31_FROM_IP: UInt32`](/documentation/Hypervisor/HV_MSR_LASTBRANCH_31_FROM_IP) The value that represents the address of the Last Branch Record 31 from Instruction Pointer (IP) register. [`var HV_MSR_LASTBRANCH_31_TO_IP: UInt32`](/documentation/Hypervisor/HV_MSR_LASTBRANCH_31_TO_IP) The value that represents the address of the Last Branch Record 31 to Instruction Pointer (IP) register. [`var HV_MSR_LASTBRANCH_INFO_0: UInt32`](/documentation/Hypervisor/HV_MSR_LASTBRANCH_INFO_0) The value that represents the address of the Last Branch Record 0 additional information register. [`var HV_MSR_LASTBRANCH_INFO_31: UInt32`](/documentation/Hypervisor/HV_MSR_LASTBRANCH_INFO_31) The value that represents the address of the Last Branch Record 31 additional information register. [`var HV_MSR_LASTBRANCH_TOS: UInt32`](/documentation/Hypervisor/HV_MSR_LASTBRANCH_TOS) The value that represents the address of the Last Branch Record Top of Stack (TOS) Register. [`var HV_MSR_LASTINT_FROM_IP: UInt32`](/documentation/Hypervisor/HV_MSR_LASTINT_FROM_IP) The value that represents the address of the Last Interrupt from Instruction Pointer (IP) Register. [`var HV_MSR_LASTINT_TO_IP: UInt32`](/documentation/Hypervisor/HV_MSR_LASTINT_TO_IP) The value that represents the address of the Last Interrupt to Instruction Pointer (IP) Register. [`var HV_MSR_LBR_SELECT: UInt32`](/documentation/Hypervisor/HV_MSR_LBR_SELECT) The value that represents the address of the Last Branch Record Filtering Select Register. [`var HV_MSR_PERF_METRICS: UInt32`](/documentation/Hypervisor/HV_MSR_PERF_METRICS) The value that represents the address of the Performance Metrics Register. --- Copyright © 2026 Apple Inc. All rights reserved. | [Terms of Use](https://www.apple.com/legal/internet-services/terms/site.html) | [Privacy Policy](https://www.apple.com/privacy/privacy-policy)