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# hv_feature_reg_t

The type that defines feature registers.

```
struct hv_feature_reg_t
```

## Topics

### Feature Registers

[`HV_FEATURE_REG_ID_AA64DFR0_EL1`](/documentation/Hypervisor/HV_FEATURE_REG_ID_AA64DFR0_EL1)

The value that identifies debug feature register 0, EL1 (DFR0_EL1).

[`HV_FEATURE_REG_ID_AA64DFR1_EL1`](/documentation/Hypervisor/HV_FEATURE_REG_ID_AA64DFR1_EL1)

The value that identifies debug feature register 1, EL1 (DFR1_EL1).

[`HV_FEATURE_REG_ID_AA64ISAR0_EL1`](/documentation/Hypervisor/HV_FEATURE_REG_ID_AA64ISAR0_EL1)

The value that identifies instruction set attribute register 0, EL1 (ISAR0_EL1).

[`HV_FEATURE_REG_ID_AA64ISAR1_EL1`](/documentation/Hypervisor/HV_FEATURE_REG_ID_AA64ISAR1_EL1)

The value that identifies instruction set attribute register 1, EL1 (ISAR_EL1).

[`HV_FEATURE_REG_ID_AA64MMFR0_EL1`](/documentation/Hypervisor/HV_FEATURE_REG_ID_AA64MMFR0_EL1)

The value that identifies memory model feature register 0, EL1(MMFR0_EL1).

[`HV_FEATURE_REG_ID_AA64MMFR1_EL1`](/documentation/Hypervisor/HV_FEATURE_REG_ID_AA64MMFR1_EL1)

The value that identifies memory model feature register 1, EL1 (MMFR1_EL1).

[`HV_FEATURE_REG_ID_AA64MMFR2_EL1`](/documentation/Hypervisor/HV_FEATURE_REG_ID_AA64MMFR2_EL1)

The value that identifies memory model feature register 2, EL1 (MMFR2_EL1).

[`HV_FEATURE_REG_ID_AA64PFR0_EL1`](/documentation/Hypervisor/HV_FEATURE_REG_ID_AA64PFR0_EL1)

The value that identifies processor feature register 0, EL1 (PFR0_EL1).

[`HV_FEATURE_REG_ID_AA64PFR1_EL1`](/documentation/Hypervisor/HV_FEATURE_REG_ID_AA64PFR1_EL1)

The value that identifies processor feature register 1, EL1 (PFR1_EL1).

[`HV_FEATURE_REG_CLIDR_EL1`](/documentation/Hypervisor/HV_FEATURE_REG_CLIDR_EL1)

The value that describes Cache Level ID Register, EL1.

[`HV_FEATURE_REG_CTR_EL0`](/documentation/Hypervisor/HV_FEATURE_REG_CTR_EL0)

The value that describes Cache Type Register, EL0.

[`HV_FEATURE_REG_DCZID_EL0`](/documentation/Hypervisor/HV_FEATURE_REG_DCZID_EL0)

The value that describes Data Cache Zero ID Register, EL0.

[`HV_FEATURE_REG_ID_AA64SMFR0_EL1`](/documentation/Hypervisor/HV_FEATURE_REG_ID_AA64SMFR0_EL1)

The value that describes Scalable Matrix Extension (SME) Feature ID Register 0.

[`HV_FEATURE_REG_ID_AA64ZFR0_EL1`](/documentation/Hypervisor/HV_FEATURE_REG_ID_AA64ZFR0_EL1)

The value that describes Scalable Vector Extension instruction (SVE) Feature ID register 0.

### Instance properties

[`rawValue`](/documentation/Hypervisor/hv_feature_reg_t/rawValue)

A 32-bit unsigned integer that represents the hardware feature registers.

### Initializers

[`init(_:)`](/documentation/Hypervisor/hv_feature_reg_t/init(_:))

Creates a new instance of the hardware feature registers.

[`init(rawValue:)`](/documentation/Hypervisor/hv_feature_reg_t/init(rawValue:))

Creates a new instance of the hardware feature registers.

## Relationships

### Conforms To

[`Hashable`](/documentation/Swift/Hashable)

[`BitwiseCopyable`](/documentation/Swift/BitwiseCopyable)

[`RawRepresentable`](/documentation/Swift/RawRepresentable)

[`Equatable`](/documentation/Swift/Equatable)

[`Sendable`](/documentation/Swift/Sendable)

---

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