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# Hypervisor Structures

## Overview

These structures allow you to interact with or control specific aspects of the operation of the Hypervisor.

## Topics

### Structures

[`struct hv_cache_type_t`](/documentation/Hypervisor/hv_cache_type_t)

The structure that describes an instruction or data cache element.

[`struct hv_vcpu_exit_exception_t`](/documentation/Hypervisor/hv_vcpu_exit_exception_t)

The structure that describes information about an exit from the virtual CPU (vCPU) to the host.

[`struct hv_apic_ctrl_t`](/documentation/Hypervisor/hv_apic_ctrl_t)

[`struct hv_apic_intr_trigger_t`](/documentation/Hypervisor/hv_apic_intr_trigger_t)

[`struct hv_apic_lvt_flavor_t`](/documentation/Hypervisor/hv_apic_lvt_flavor_t)

[`struct hv_apic_state`](/documentation/Hypervisor/hv_apic_state)

[`struct hv_apic_state_ext_t`](/documentation/Hypervisor/hv_apic_state_ext_t)

[`struct hv_atpic_state`](/documentation/Hypervisor/hv_atpic_state)

[`struct hv_atpic_state_ext_t`](/documentation/Hypervisor/hv_atpic_state_ext_t)

[`struct hv_gic_distributor_reg_t`](/documentation/Hypervisor/hv_gic_distributor_reg_t)

[`struct hv_gic_icc_reg_t`](/documentation/Hypervisor/hv_gic_icc_reg_t)

[`struct hv_gic_ich_reg_t`](/documentation/Hypervisor/hv_gic_ich_reg_t)

[`struct hv_gic_icv_reg_t`](/documentation/Hypervisor/hv_gic_icv_reg_t)

[`struct hv_gic_intid_t`](/documentation/Hypervisor/hv_gic_intid_t)

[`struct hv_gic_msi_reg_t`](/documentation/Hypervisor/hv_gic_msi_reg_t)

[`struct hv_gic_redistributor_reg_t`](/documentation/Hypervisor/hv_gic_redistributor_reg_t)

[`struct hv_ioapic_state`](/documentation/Hypervisor/hv_ioapic_state)

[`struct hv_ioapic_state_ext_t`](/documentation/Hypervisor/hv_ioapic_state_ext_t)

[`struct hv_sme_p_reg_t`](/documentation/Hypervisor/hv_sme_p_reg_t)

[`struct hv_sme_z_reg_t`](/documentation/Hypervisor/hv_sme_z_reg_t)

[`struct hv_vcpu_sme_state_t`](/documentation/Hypervisor/hv_vcpu_sme_state_t)

[`struct hv_vm_exitinfo_t`](/documentation/Hypervisor/hv_vm_exitinfo_t)


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