Architecture

This chapter describes the architecture of the iBook computer.

Block Diagram and Buses

This section is an overview of the major ICs and buses on the computer’s main logic board.

Block Diagram

Figure 2-1 is a simplified block diagram of the main logic board. The diagram shows the input and output connectors, the main ICs, and the buses that connect them together.

Figure 2-1  Block diagram
Block diagram

Main ICs and Buses

The architecture of the iBook computer is designed around the PowerPC G3 microprocessor and the custom Pangea memory and I/O controller. The Pangea IC occupies the center of the block diagram.

The microprocessor is connected to the Pangea IC by a 60x bus with 64 data lines and a bus clock speed of 100 MHz. The Pangea IC has other buses that connect with the Boot ROM, the main system RAM, the graphics IC, and the Ethernet and FireWire PHY ICs. Each of the components listed here is described in one of the following sections. The buses implemented by the Pangea IC are summarized in Table 2-1, which is in the section Memory and I/O Device Controller.

Microprocessor and Cache

The microprocessor communicates with the rest of the system by way of a 100-MHz, 64-bit 60x bus to the Pangea IC. The backside cache is built into the microprocessor.

Power PC G3 Microprocessor

The microprocessor used in the iBook computer is a PowerPC G3. It has several features that contribute to superior performance, including:

  • on-chip level 1 (L1) caches, 32 KB each for instruction cache and data cache

  • an on-chip second level (L2) cache consisting of 512 KB with a clock speed ratio of 1:1

  • a microprocessor core optimized for Mac OS applications

The G3 microprocessor in the iBook computer normally runs at a clock speed of 700 or 800 MHz. The Power Stepping feature slows the clock speed to save power when the computer is idle. See Power Stepping.

L2 Cache

The data storage for the L2 cache consists of 512 KB of fast static RAM that is built into the microprocessor chip along with the cache controller. The built-in L2 cache runs at the same clock speed as the microprocessor.

Memory and I/O Device Controller

The Pangea memory controller and I/O device controller IC provides cost and performance benefits by combining many functions into a single IC. It contains the memory controller, the PCI bus bridge, the Ethernet and FireWire interfaces, and the AGP port.

In addition to the buses listed in Table 2-1, the Pangea IC also has separate interfaces to the physical layer (PHY) ICs for Ethernet and FireWire and an I2C interface that is used for configuring the memory subsystem.

Table 2-1  Buses supported by the Pangea IC

Name of bus

Destinations

Width of data path

Bus clock speed

60x bus

Microprocessor

64 bits

100 MHz

Memory bus

System RAM

64 bits

100 MHz

AGP 2X bus

Graphics IC

32 bits

66 MHz

Ultra DMA IDE bus

Hard drive and CD or DVD drive

16 bits

33 MHz

The Pangea IC provides DB-DMA (descriptor-based direct memory access) support for the I/O channels. The DB-DMA system provides a scatter-gather process based on memory resident data structures that describe the data transfers. The DMA engine is enhanced to allow bursting of data files for improved performance.

The microprocessor is described in its own section. The following sections describe the other subsystems that are connected to the Pangea IC.

System RAM

The memory subsystem in the iBook computer consists of 128 MB of SDRAM soldered on the main logic board and one expansion slot for an SO-DIMM. In some models, the expansion slot is occupied by a 128-MB SO-DIMM for a total of 256 MB of system RAM.

The data bus to the RAM and DIMM is 64 bits wide, and the memory interface is synchronized to the 60x bus interface at 100 MHz. See also RAM Expansion.

Boot ROM

The boot ROM includes the hardware-specific code and tables needed to start up the computer, to load an operating system, and to provide common hardware access services.

The boot ROM is connected to the card slot interface of the Pangea IC. The boot ROM is a 1 M by 8 bit flash device and can be updated in the field.

Ethernet Controller

The Pangea IC includes an Ethernet media access controller (MAC) that implements the link layer. As a separate channel connected directly to the Pangea logic, it can operate at its full capacity without degrading the performance of other peripheral devices. The Pangea IC provides DB-DMA support for the Ethernet interface.

The controller is connected to a PHY interface IC that is capable of operating in either 10-BaseT or 100-BaseT mode. The actual speed of the link is automatically negotiated by the PHY and the bridge or router to which it is connected. For information about the connector and the operation of the port, see Ethernet Port.

FireWire Controller

The Pangea IC includes an IEEE 1394 FireWire controller with a maximum data rate of 400 Mbits (50MBytes) per second. The Pangea IC provides DMA (direct memory access) support for the FireWire interface. The FireWire controller complies with the Open Host Controller Interface (OHCI) specification.

The controller IC implements the FireWire link layer. A physical layer IC, called a PHY, implements the electrical signalling protocol of the FireWire interface. The PHY is the interface to the external connector. For information about the connector and the operation of the port, see FireWire Port.

Graphics IC

The graphics IC is an ATI Mobility Radeon 7500. It provides video for both the internal flat panel display and an external video display. The signals to the external display can be either VGA, composite video, or S-video; for more information, seeExternal Display Port.

The Mobility Radeon IC includes either 16 MB of DDR SDRAM on the CD-ROM model or 32 MB of DDR SDRAM on the Combo drive models. The graphics IC supports a display size of 1024 by 768 pixels and also has a scaling mode that displays a 640-by-480 or 800-by-600 pixel image on the full screen.

The Mobility Radeon 7500 IC also has a 3D graphics engine for fast rendering of 3D objects.

The signal generated for the flat panel display is simultaneously available for an external display. The external display mirrors the built-in display. For more information, see External Display Port.

Because the graphics IC uses the AGP bus, it can use part of main memory as additional graphics storage. The computer’s virtual memory system organizes main memory as randomly-distributed 4 KB pages, so DMA transactions for more than 4 KB of data would have to perform scatter-gather operations. To avoid this necessity for graphics storage, the AGP logic in the Pangea IC uses a graphics address remapping table (GART) to translate a linear address space for AGP transactions into physical addresses in main memory.

Ultra DMA IDE Bus

The Pangea IC provides an Ultra DMA IDE (integrated drive electronics) channel that is connected to the internal hard disk drive and the CD or DVD drive. The Ultra DMA IDE interface, also called Ultra-DMA/33 and ATA-5, is an improved version of the EIDE interface. The Pangea IC provides DB-DMA (descriptor-based direct memory access) support for the Ultra DMA interface.

The internal hard disk drive is connected as device 0 (master) in an ATA Device 0/1 configuration. The CD or DVD drive is connected as device 1 (slave). Digital audio data from the CD or DVD drive is processed by the Sound Manager and then sent out through the Pangea IC to the sound IC.

USB Interface

The Pangea IC implements two independent USB controllers (root hubs), each of which is connected to one of the ports on the side panel of the computer. The use of two independent controllers allows both USB ports to support high data rate devices at the same time with no degradation of their performance. If a user connects a high-speed (12 Mbps) device to one port and another high-speed device to the other, both devices can operate at their full data rates.

The external USB connectors support USB devices with data transfer rates of 1.5 Mbps and 12 Mbps. For more information, see USB Ports.

USB devices connected to the iBook computer are required to support USB-suspend mode as defined in the USB specification. Information about the operation of USB-suspend mode on Macintosh computers is included in the Mac OS USB DDK API Reference. To obtain that document, please see the references at USB Interface.

The USB ports on the iBook computer comply with the Universal Serial Bus Specification 1.1 Final Draft Revision. The USB controllers comply with the Open Host Controller Interface (OHCI) specification.

Modem Support

The internal modem is connected to an internal USB port. The Pangea IC provides DB-DMA support for the modem interface. The modem provides digital call progress signals to the Tumbler sound circuitry.

The internal modem is a separate module that contains the datapump IC and the interface to the telephone line (DAA). The controller functions are performed by the main processor. See Internal Modem

Sound Circuitry

The iBook computer has sound circuitry, called Tumbler, that is connected to the Pangea IC by a standard I2S bus. The Pangea IC provides DB-DMA (descriptor-based direct memory access) support for the I2S port.

The sound circuitry includes a signal processing IC that handles the equalization and volume control functions and a codec IC that performs A-to-D and D-to-A conversion.

All audio is handled digitally inside the computer. The Tumbler circuitry performs digital-to-analog conversion for the audio signals to the internal speakers and the headphone mini-jack. The Tumbler circuitry also provides parametric equalization for the internal speakers.

Modem progress audio is connected as a digital input to the sound circuitry so that it can be mixed into the sound output stream. The modem progress audio is processed as play-through only, not as a digital sound source.

The iBook computer has no dedicated sound input jack. The sound system supports the built-in microphone and other sound input by way of a USB microphone or other USB audio device. For information about sound system operation, see Sound System.

Power Control IC

The power manager IC in the iBook computer is a Mitsubishi M16C/62F microprocessor, also called the PMU99. It operates with its own RAM and ROM. The functions of the PMU99 include:

  • controlling the sleep and power on and off sequences

  • controlling power to the other ICs

  • monitoring the battery charge level

  • controlling battery charging

  • supporting the interface to the built-in keyboard and trackpad

The iBook computer can operate from a 15-volt power outlet on an airliner, however for safety reasons the computer will not allow battery charging. In order for the computer to detect the connection to airline power, the airline power cable should have a sense resistor of 24.3K ohms connected between the power plug's shell and ground.

The PMU99 also provides the hardware interface to the keyboard and trackpad. Software in the PMU99 IC scans the keyboard and receives data from the trackpad, then sends the data to the system in packets like those from the ADB. To the system, the keyboard and trackpad behave as if they were ADB devices.

AirPort Card

The AirPort Card shares the card slot interface to the Pangea IC with the boot ROM.

The AirPort Card contains a media access controller (MAC), a digital signal processor (DSP), and a radio-frequency (RF) section. The card has a connector for the cable to the antennas, which are built into the computer’s case.

The AirPort Card is based on the IEEE 802.11b standard. The card transmits and receives data at up to 11 Mbps and is compatible with older 802.11-standard systems that operate at 2 or 1 Mbps. For information about its operation, see AirPort Card.