PowerPC G4 Microprocessor

The PowerPC G4 microprocessors used in the PowerMac G4 computer have many powerful features, including a pipelined system bus called MaxBus.

The PowerPC G4 used in the PowerMac G4 computer has the following features:

• 32-bit PowerPC implementation

• superscalar PowerPC core

• Velocity Engine (AltiVec technology): 128-bit-wide vector execution unit

• high bandwidth MaxBus with 36 address bits and 64 data bits

• fully symmetric multiprocessing capability

• dual 32 KB instruction and data caches (level 1)

• built-in 256 KB backside L2 cache

• support for up to 2 MB backside L3 cache

• on-chip L3 tag storage

For more information, see the reference at PowerPC G4 Microprocessor.

Cache Memory

In addition to the 256 KB level 2 (L2) cache built into the PowerPC G4 microprocessor, the processor module also has an external level 3 (L3) cache for each microprocessor. The L3 cache consists of 1 or 2 MB of double data rate (DDR) SDRAM. The clock frequency and clock ratio for the L3 cache are shown below.

Processor Bus

The processor bus is a 133 or 167 MHz bus connecting the processor module to the U2 IC. The bus has 64-bit wide data and 32-bit wide addresses. The bus uses MaxBus protocols, supported by the U2 IC.

The MaxBus protocol includes enhancements that improve bus efficiency and throughput over the 60x bus. The enhancements include

• out-of-order completion

• address bus streaming

• intervention

Out-of-order completion allows the memory controller to optimize the data bus efficiency by transferring whichever data is ready, rather than having to pass data across the bus in the order the transactions were posted on the bus. This means that a fast DDR SDRAM read can pass a slow PCI read, potentially enabling the processor to do more before it has to wait on the PCI data.

Address-bus streaming allows a single master on the bus to issue multiple address transactions back-to-back. This means that a single master can post addresses at the rate of one every two clocks, rather than one every three clocks, as it is in the 60x bus protocol.

Intervention is a cache-coherency optimization that improves performance for dual-processor systems. If one processor modifies some data, that data first gets stored only in that processor’s cache. If the other processor then wants that data, it needs to get the new modified values. In previous systems, the first processor must write the modified data to memory and then the second processor can read the correct values from memory. With intervention, the first processor sends the data directly to the second processor, reducing latency by a factor of ten or more.

Main Memory Bus

For the 1 GHz PowerMac G4 computer, the main memory bus connects the main memory to the U2 IC via a 133 MHz, 64-bit data bus. For the 1.25 GHz or 1.42 GHz configurations, the main memory bus connects the main memory to the U2 IC via a 167 MHz, 64-bit data bus. For the 1 GHz computer, the minimum speed DDR is 2x133 MHz, which is DDR 266 (PC2100). For the 1.25 GHz and 1.42 GHz computers, the minimum speed DDR is 2x167 MHz, which is DDR 333 (PC2700).

Main memory is provided by up to four 133 MHz DDR 266 or 167 MHz DDR 333 DIMMs using double data rate SDRAM devices. Supported DIMM sizes are 256 and 512 MB (also is 128 MB- and 1GB-capable). The memory slots accept four 512-MB DIMMs (also is capable of 2-1GB) for a maximum memory size of 2 GB. For more information about memory DIMMs, see RAM Expansion.

The address bus is connected to all four DIMM slots, so the total number of address bus loads to the controller IC can vary from one to eight. The data bus is connected through four switches, one for each DIMM slot. Only one switch is selected at a time, so the data bus presents either one or two loads, depending on whether the selected DIMM has one or two banks. The data switches have no drive capability; they are either low or high impedance, depending on whether they are selected or not.

Ultra ATA/100 Interface

The U2 IC implements a single Ultra ATA/100 hard disk interface and can accommodate one or two internal hard drives. For information about the drive bays, see Hard Disk Drives.

The KeyLargo IC provides DB-DMA (descriptor-based direct memory access) support for the Ultra ATA/66 interface.

Accelerated Graphics Port Bus

The accelerated graphics port (AGP) bus is a 66 MHz, 32-bit bus connecting the AGP card to the U2 IC. Data is transmitted at both edges of the clock and appears at a rate 4x the clock. The bus is an AGP-4x bus supporting peak transfers of 512 MB/s.

The AGP bus is a superset of the PCI bus, with the addition of separate address lines so it does not multiplex address and data when running in AGP mode. Having a separate address bus allows the AGP bus to pipeline addresses, thereby improving performance.

To further improve the performance of the AGP bus, the U2 IC supports a graphics address remapping table (GART). Because the virtual memory system organizes main memory as randomly distributed 4 KB pages, DMA transactions for more than 4 KB of data must perform scatter-gather operations. To avoid this necessity for AGP transactions, the GART is used by the AGP bridge in the U2 to translate a linear address space for AGP transactions into physical addresses in main memory.

For more information on the graphics cards installed in the AGP slot, refer to Graphics Cards.

PCI Bus

The 33-MHz, 64-bit PCI bus connects the U2 IC to the boot ROM, the KeyLargo I/O controller, the PCI slots, and the USB controllers. The U2 IC used in the PowerMac G4 computer supports the PCI write combining feature. This feature allows sequential write transactions involving the Memory Write or Memory Write and Invalidate commands to be combined into a single PCI transaction. The memory write transactions being combined must be sequential, ascending, and non-overlapping PCI addresses. Placing an eieio or sync command between the write commands prevents any write combining.

For more information on the PCI bus, refer to PCI Expansion Slots .

Wireless LAN Module

The optional AirPort Extreme wireless LAN module connects via the PCI interface.

The AirPort Extreme Card wireless LAN module contains a media access controller (MAC), a digital signal processor (DSP), and a radio-frequency (RF) section. The module has a connector for the cable to the antennas, which are built into the computer’s case.

The AirPort Extreme Card is based on the IEEE draft specification of the 802.11g standard. The card transmits and receives data at up to 54 Mbps and is compatible with 802.11b-standard 11 Mbps systems and older 802.11b-standard systems. For information about its operation, see AirPort Extreme Card (Optional).

The optional fully-integrated Bluetooth connectivity comes off the USB bus, see USB Interface and Bluetooth Technology (Optional).

Modem Slot Support

The KeyLargo IC has a traditional Macintosh serial port and a USB port, however, modem support is via the USB controller rather than KeyLargo (see PCI USB Controller.

The KeyLargo IC provides DB-DMA (descriptor-based direct memory access) support for the modem slot interface.

The internal hardware modem is a separate module that contains a modem controller IC, a data pump, and the interface to the telephone line (DAA). For more information about the modem, see Internal Modem.

Boot ROM

The boot ROM consists of 1 MB of on-board flash EPROM. The boot ROM includes the hardware-specific code and tables needed to start up the computer using Open Firmware, to load an operating system, and to provide common hardware access services.

Ethernet Controller

The U2 IC includes an Ethernet media access controller (MAC). As a separate I/O channel on the U2 IC, it can operate at its full capacity without degrading the performance of other peripheral devices. The U2 IC provides DMA support for the Ethernet interface.

The MAC implements the link layer. It is connected to a PHY interface IC that provides 10-BaseT, 100-BaseT, or 1000-BaseT operation over a standard twisted-pair interface. The Ethernet port is auto-sensing and self-configuring to allow use of either a cross-over or straight-through cable. The operating speed of the link is automatically negotiated by the PHY and the bridge or router to which the Ethernet port is connected. For information about the port, see Ethernet Port .

FireWire Controllers

The U2 IC includes an IEEE 1394b FireWire 800 controller with a maximum data rate of 800 Mbps (100 MBps). The IC is backwards-compatible with 1394a and FireWire 400. The U2 IC provides DMA (direct memory access) support for the FireWire interface.

The controller in the U2 IC implements the FireWire link layer. A physical layer IC, called a PHY, implements the electrical signaling protocol of the FireWire interface and provides the electrical signals to the ports. For more information, see FireWire Ports.

DMA Support

The KeyLargo IC provides DB-DMA (descriptor-based direct memory access) support for the following I/O channels:

• Ultra ATA/66

• EIDE interface

• Communication slot interface

• IIS channel to the sound subsystem

The DB-DMA system provides a scatter-gather process based on memory-resident data structures that describe the data transfers. The DMA engine is enhanced to allow bursting of data files for improved performance.

Interrupt Support

The interrupt controller for the PowerMac G4 system is an MPIC cell in the KeyLargo IC. In addition to accepting all the KeyLargo internal interrupt sources, the MPIC controller accepts external interrupts from dedicated interrupt pins and serial interrupts from the U2 serial interrupt stream. The signals from the U2 IC are synchronized to the operation of the MPIC circuitry, so there is no additional interrupt latency on the U2 interrupts.

USB Interface

The KeyLargo IC has two independent USB root hubs, which are not connected in the PowerMac G4. Application code that was targeted to these ports in previous models of the PowerMac G4 will not work in this version.

The USB interface is via the PCI USB controller; see PCI USB Controller.

Ultra ATA/66 Interface

The KeyLargo IC implements a single Ultra ATA/66 hard disk interface. This interface can accommodate one or two internal hard drives. The KeyLargo IC provides DB-DMA (descriptor-based direct memory access) support for the Ultra ATA/66 interface.

For information about the drive bays, see Hard Disk Drives.

Enhanced IDE Interface

In the PowerMac G4 computer, the KeyLargo IC provides an enhanced IDE (EIDE) interface. The EIDE interface supports the removable media drives mounted behind the front panel, an optical drive, and second optical drive.

For information about specific drives, see Optical Drives.

The KeyLargo IC provides DB-DMA (descriptor-based direct memory access) support for the EIDE interface.

Sound Circuitry

The sound circuitry, called Snapper, is connected to the KeyLargo IC by a standard IIS (inter-IC sound) bus. The KeyLargo IC provides DB-DMA (descriptor-based direct memory access) support for the IIS port.

The core of the Snapper circuitry is an IC that performs digital audio processing and codec functions. The digital audio processing functions include output equalization, dynamic range compression, and volume control. The equalization and dynamic range control functions are set to fixed values to equalize a set of Apple Pro Speakers and the internal speakers. Those functions are bypassed for signals sent to the audio output jacks.

The codec functions include one stereo input pair and three stereo output pairs.

Stereo signals from the audio input jack are routed to an analog line input buffer that drives the internal A/D converter.

Digital audio data from the KeyLargo IC drives the internal D/A converter. Analog audio signals from the D/A converter are routed to the headphone jack, the line output jack, and an audio power amplifier.

The audio power amplifier drives the internal speaker, the Apple Pro Speakers, and front headphone. When Apple Pro Speakers are connected to the external speaker jack or headphones are installed, the internal speaker is muted.

For a description of the features of the sound system, see Sound System .

Power Controller

The power management controller in the PowerMac G4 computer is a microcontroller called the PMU99. It supports new modes of power management that provide significantly lower power consumption than previous systems. For more information, see Power-Saving Modes.