PowerPC G5 Microprocessor

The PowerPC G5 used in the Power Mac G5 computer has the following features:

• 64-bit PowerPC implementation with 42-bit physical memory addressing

• core runs at twice the bus speed

• superscalar execution core supporting more than 200 in-flight instructions

• two independent double-precision floating point units

• Velocity Engine: 128-bit-wide vector execution unit

• 64K L1 instruction cache, 32K L1 data cache per processor

• fully symmetric multiprocessing capability

• built-in 512 KB backside L2 cache per processor

• two independent, unidirectional 1.0 GHz to 1.35 GHz frontside buses each supporting up to 10.8 GBps data throughput per processor

For more information, see the reference at PowerPC G5 Microprocessor.

Processor Bus

The processor bus is a 1 GHz, 1.15 GHz or 1.35 GHz bus connecting the processor module to the U3H IC. The bus has 64-bit (32-bit in and 32-bit out) wide data and 36-bit wide addresses.

The Power Mac G5 system controller is built with 130-nanometer, SOI technology. This super-efficient point-to-point architecture provides each subsystem with dedicated bandwidth to main memory. The Power Mac G5 uses separate processor boards with each PowerPC G5 processor; two processor boards are used for the Power Mac G5’s dual processor design. The U3H I/O implements two independent processor interfaces. The processor clock is derived from a PLL which multiplies the reference clock by preset intervals of 8 times.

Out-of-order completion allows the memory controller to optimize the data bus efficiency by transferring whichever data is ready, rather than having to pass data across the bus in the order the transactions were posted on the bus. This means that a fast DDR SDRAM read can pass a slow PCI read, potentially enabling the processor to do more before it has to wait on the PCI data.

Intervention is a cache-coherency optimization that improves performance for dual-processor systems. If one processor modifies some data, that data first gets stored only in that processor’s cache. If the other processor then wants that data, it needs to get the new modified values.

Main Memory Bus

The Power Mac G5 computer main memory bus connects the main memory to the U3H IC via the 128-bit data bus. The memory modules are 400 MHz (PC3200) DDR SDRAM DIMMs with a per system maximum of 4 GB or 8 GB, depending on the configuration.

Standard supported DIMM sizes are 128, 256, 512 MB, and 1 GB. The DIMMs must be unbuffered and installed in pairs of the same size.

For more information about memory DIMMs and installation, see RAM Expansion.

Accelerated Graphics Port Bus

The accelerated graphics port (AGP 8x Pro) bus is a 266/533 MHz, 32-bit bus connecting the AGP card to the U3H IC. DDR data is transmitted at both edges of the clock for peak transfers of 2.1 GBps.

The AGP bus is an enhanced PCI bus with extra functionality to burst texture data and other graphics across the port up to 8 times faster than a 66 MHz PCI port. The Power Mac G5 computer’s AGP implementation is compatible with version 3 of the AGP specification and with the Pro version of AGP. AGP 3.0 enables deeply pipelined memory read and write operations and demultiplexing of address and data on the bus.

To further improve the performance of the AGP bus, the U3H IC supports a graphics address remapping table (GART). Because the virtual memory system organizes main memory as randomly distributed 4 KB pages, DMA transactions for more than 4 KB of data must perform scatter-gather operations. To avoid this necessity for AGP transactions, the GART is used by the AGP bridge in the U3H to translate a linear address space for AGP transactions into physical addresses in main memory.

The U3H IC also supports a DMA Address Relocation Table (DART) that provides the same functions for AGP as does the GART, except that the functions are for devices attached to HyperTransport. Most device drivers do not require special knowledge of the DART because IOKit will configure it automatically if the driver uses IOMemoryDescriptors.

For more information on the graphics cards installed in the AGP slot, refer to Graphics Cards.

Internal PCI Bus

An internal 33 MHz, 64-bit PCI bus connects the K2 I/O controller to the boot ROM, the AirPort Extreme Card slot, and the USB controller. The U3H IC used in the Power Mac G5 computer supports the PCI write combining feature. This feature allows sequential write transactions involving the Memory Write or Memory Write and Invalidate commands to be combined into a single PCI transaction. For memory write transactions to be combined, they must be sequential, ascending, and non-overlapping PCI addresses. Placing an eieio or sync command between the write commands prevents any write combining.

For more information on the PCI bus, refer to PCI or PCI-X Expansion Slots.

PCI or PCI-X Expansion Slots

In some configurations, the Power Mac G5 computer provides three 64-bit 33 MHz PCI slots that interface to the K2 I/O and share the bus with the USB controller.

In some configurations, the Power Mac G5 computer provides three PCI-X slots that interface to the HyperTransport bus via the PCI-X bridge. One slot runs at a maximum of 133 MHz and two slots run at a maximum of 100 MHz. The 133 MHz slot can support a maximum burst bandwidth of 1064 MBps, based on 64 bits times 133 MHz. The two 100 MHz slots can support a combined bandwidth of 800 MBps. It is recommended that the highest bandwidth card be inserted in the 133 MHz PCI-X slot labeled slot 4.

Each slot has room for a full size 12.335-inch or short 6.926-inch card. The slots are numbered from 2 to 4 on back panel, on the PCB, and in the Apple System Profiler. Slot one is the AGP.

The connectors to the PCI or PCI-X slots are 3.3 V keyed and support 32-bit and 64-bit buses. The connectors include a PME signal which allows a PCI card to wake the computer from sleep.

The slots (12.335 inch) have a capture feature which is at the end of the slot. If a card exceeds the short length it is recommended that the long length be used rather than an intermediate length, to assure the card stays secure if and when the system is in shipment.

For more information, refer to PCI or PCI-X Expansion Slots.

DMA Support

The K2 IC provides DB-DMA (descriptor-based direct memory access) support for the following I/O channels:

• Ultra ATA/100

• Ethernet interface

• FireWire interface

• I2S channel to the sound subsystem

• Serial ATA

The DB-DMA system provides a scatter-gather process based on memory-resident data structures that describe the data transfers. The DMA engine is enhanced to allow bursting of data files for improved performance.

Wireless LAN Module

The AirPort Extreme Card wireless LAN module (via the PCI USB controller) contains a media access controller (MAC), a digital signal processor (DSP), and a radio-frequency (RF) section. The module is wired to an antenna port on the rear of the computer.

The AirPort Extreme Card is compliant with the IEEE 802.11g standard. The card transmits and receives data at up to 54 Mbps and is compatible with Apple AirPort systems as well as other 802.11b and 802.11g Wi-Fi certified products. For information about its operation, see AirPort Extreme Card.

The internal Bluetooth module connectivity comes off the PCI USB controller. See Bluetooth Technology for more information.

Modem Slot Support

The K2 IC supports the modem and provides DB-DMA (descriptor-based direct memory access) support for the modem slot interface. The modem is connected via an I2S interface.

The internal hardware modem is a separate module that contains a modem controller IC, a data pump, and the interface to the telephone line (DAA). For more information about the modem, see Internal Modem.

Boot ROM

The boot ROM consists of 1 MB of on-board flash EEPROM. The boot ROM includes the hardware-specific code and tables needed to start up the computer using Open Firmware, to load an operating system, and to provide common hardware access services.

Ethernet Controller

The K2 IC includes an Ethernet media access controller (MAC) and PHY. As a separate I/O channel on the K2 IC, it can operate at its full capacity without degrading the performance of other peripheral devices.

The MAC implements the link layer. It is connected to a PHY that is internal to K2 and provides 10Base-T/UTP, 100Base-TX, or 1000Base-T operation over a standard twisted-pair interface. The Ethernet port is auto-sensing and self-configuring to allow use of either a cross-over or straight-through cable. The operating speed of the link is automatically negotiated by the PHY and the bridge, router, hub, switch, or other Mac or PC to which the Ethernet port is connected.

For information about the Ethernet port, see Ethernet Port.

FireWire Controllers

The K2 IC includes a FireWire controller that supports both IEEE 1394b (FireWire 800) with a maximum data rate of 800 Mbps (100 MBps) and IEEE 1394a (FireWire 400) with a maximum data rate of 400 Mbps (50 MBps). The IC is backwards-compatible with 1394a (FireWire 400). The K2 IC provides DMA (direct memory access) support for the FireWire interface.

The controller in the K2 IC implements the FireWire link layer. A physical layer IC, called a PHY, implements the electrical signaling protocol of the FireWire interface and provides the electrical signals to the ports.

For more information, see FireWire Ports.

Interrupt Support

The interrupt controller is an MPIC cell in the K2 IC. In addition to accepting internal interrupt sources from the I/O, the MPIC controller accepts internal interrupts from U3H and dedicated interrupt pins.

USB Interface

The K2 IC has two independent USB OHCI controllers. The external USB interface is via the PCI USB controller; see PCI USB Controller.

Serial ATA Interface

Based on the Serial ATA 1.0 specification, Serial ATA (SATA) is a disk-interface technology that delivers up to 1.5 Gbps of performance to each independent drive bus on the Power Mac G5 computer. It provides a scalable, point-to-point connection that allows multiple ports to be aggregated into a single controller. Serial ATA uses a thin, point-to-point cable connection that enables easy routing within a system, avoiding master/slave, daisy-chaining, and termination issues and enabling better airflow within a system.

The K2 IC implements two Serial ATA revision one ports, each of which accommodates one independent internal hard drive.

For information about the drive bays, see Hard Disk Drives.

Ultra DMA ATA/100 Interface

The K2 IC provides an Ultra DMA ATA/100 interface to support the optical drive. For information about specific drives, see Disk Drives.

Sound System Overview

The sound circuitry is connected to the K2 IC by a standard I2S (inter-IC sound) bus. The K2 IC provides DB-DMA (descriptor-based direct memory access) support for the I2S port.

The Power Mac G5 circuitry consists of two main components: an analog audio CODEC IC and a digital audio CODEC IC. The analog audio CODEC IC includes an A/D converter, a D/A converter, and digital audio processing functions. The digital audio processing functions include output equalization, dynamic range compression, and volume control. The equalization and dynamic range control functions are set to fixed values to equalize the internal speaker. Those functions are bypassed for signals sent to the audio output jacks.

Stereo signals from the audio input jack are routed to an analog line input buffer that drives the internal A/D converter in the analog CODEC. The output of the A/D converter is routed to the K2 IC over the I2S bus.

Digital audio data from the K2 IC is routed to the D/A converter on the analog audio CODEC over the I2S bus. The analog audio output from the D/A converter is routed to separate amplifiers that drive the line output, headphone output, and internal speaker.

The digital audio CODEC IC includes an S/PDIF (Sony/Phillips Digital Interface) digital audio receiver, a sample rate converter (SRC), a phase-locked loop (PLL), and an S/PDIF digital audio transmitter.

The S/PDIF input can operate in synchronous and asynchronous modes. In synchronous mode, the PLL in the digital audio CODEC locks on to the incoming S/PDIF data rate and drives the audio system clocks in the Power Mac G5, allowing bit-accurate data processing of the S/PDIF input data. In asynchronous mode, the incoming S/PDIF data passes through the SRC, where it is converted to the output sample rate of the Power Mac G5, allowing the Power Mac G5 to play audio at a fixed output sample rate while accepting S/PDIF input data over a wide frequency range. The audio data from the S/PDIF receiver is routed to the K2 IC over the I2S bus.

Digital audio data from the K2 chip is routed to the S/PDIF output transmitter in the digital audio CODEC over the I2S bus. The Power Mac G5 sends and receives S/PDIF audio data over TOSLink optical connectors.

Analog audio I/O is not independent of digital audio I/O on the Power Mac G5. Audio input can come from either the line input or the S/PDIF input, but not both at the same time. Audio output can be played simultaneously on the line out, headphones output, and S/PDIF output. However, these audio streams are not independent.

The speaker output is mutually exclusive from the line out, headphones out and S/PDIF outputs. If the speaker output is selected, the line output, the headphones output and the S/PDIF output are disabled. If any of the line output, the headphones output, or the S/PDIF output are selected, the speaker output is disabled.

When the speaker output is active, the digital audio processing functions in the analog CODEC are used to implement output equalization for the internal speaker, resulting in improved sound quality from the internal speaker.

For more detail on the audio, see Audio.

Power Controller

The power management controller in the Power Mac G5 computer is a microcontroller called the PMU99. It supports new modes of power management that provide significantly lower power consumption than earlier systems. The Power Mac G5 also utilizes a service processor unit and a fan controller unit (refer to Fan Controller).

For more information on power management strategy, see Power Management.