PowerPC G5 Microprocessor

The PowerPC G5 used in the Xserve G5 has the following features:

• 64-bit PowerPC implementation with 42-bit physical memory addressing

• core runs at twice the bus speed

• superscalar execution core supporting more than 200 in-flight instructions

• two independent double-precision floating point units

• Velocity Engine: 128-bit-wide vector execution unit

• 64K L1 instruction cache, 32K L1 data cache per processor

• fully symmetric multiprocessing capability

• built-in 512KB L2 cache per processor

• independent, unidirectional frontside bus for each processor running at half the speed of the processor, each supporting a minimum of 8 GBps data throughput per processor

To find more information, see the reference at PowerPC G5 Microprocessor.

Cache Memory

The Xserve G5 has 512 KB L2 cache per processor built into the PowerPC G5 microprocessor.

Dual Processors

The dual-processor configurations of the Xserve G5 have two processor cards containing a PowerPC G5 processor. The dual-processor configurations allow applications that support multitasking to about double their performance.

Processor Bus

The processor bus runs at half the speed of the processor and connects the processor module to the U3H IC. The bus has 64-bit wide data and 36-bit wide addresses.

The Xserve G5 system controller is built with 130-nanometer, SOI technology, providing each subsystem with dedicated bandwidth to main memory. The Xserve G5 uses separate processor boards with each PowerPC G5 processor; two processor boards are used for dual processor systems. The U3H I/O implements two independent processor interfaces. The processor clock rate is up to 2.3 GHz in and connects to the U3H I/O through the Apple Processor Interface (API). The processor clock is derived from a PLL which multiplies the reference clock by preset intervals of 8 times.

Out-of-order completion allows the memory controller to optimize the data bus efficiency by transferring whichever data is ready, rather than having to pass data across the bus in the order the transactions were posted on the bus. This means that a fast DDR SDRAM read can pass a slow PCI read, potentially enabling the processor to do more before it has to wait on the PCI data.

Intervention is a cache-coherency optimization that improves performance for dual-processor systems. If one processor modifies some data, that data first gets stored only in that processor’s cache. If the other processor then wants that data, it needs to get the new modified values.

Main Memory Bus

The Xserve G5 main memory bus connects the main memory to the U3H IC via the 64-bit data bus. Main memory is provided by up to eight ECC DDR400 (PC3200) SDRAM DIMMs. Supported DIMM sizes are 256 MB, 512 MB, and 1 GB. The DIMMs must be unbuffered and installed in pairs of the same size. The memory slots accept a maximum of eight 1 GB DIMMs for memory size of 8 GB.

For more information about memory DIMMs, see RAM Expansion.

PCI or PCI-X Expansion Slots

The Xserve G5 provides two open, user-accessible PCI-X slots via Bus A of the HyperTransport bus. Bus B implements the high speed, dual channel, on-board, gigabit Ethernet controller. To connect a monitor to the Xserve G5, Bus A also supports a build-to-order graphics card; see Optional Graphics Card.

Each user-accessible slot on Bus A has room for a full size 12.335-inch or short 6.926-inch card, holding a maximum of two full size cards.

The expansion slots on Bus A accommodate 32-bit and 64-bit PCI and PCI-X cards. PCI-X cards need to be compatible with Mac OS X and with PCI-X 1.0 standards. PCI cards need to be compatible with Mac OS X and with Xserve G5 systems. Supported PCI and PCI-X speeds are: 33 MHz, 66 MHz, 100 MHz, or 133 MHz. The 133 MHz PCI-X option is available only when one card is installed. If a second card is installed, the 133 MHz PCI-X card operates at a maximum of 100 MHz. If two cards are installed, both cards operate at the speed of the slower card. If a PCI card is installed in either slot, both slots will operate as PCI slots.

The connectors to the PCI-X slots are 3.3 V keyed and support 32-bit and 64-bit buses. The connectors include a PME signal which allows a PCI card to wake the computer from sleep. Maximum power consumption for both expansion slots is 25 W (15 W top slot, 10 W bottom slot).

The slots (12.335 inch) have a capture feature which is at the end of the slot. If a card exceeds the short length it is recommended that the long length be used rather than an intermediate length, to assure the card stays secure if and when the system is in shipment.

The U3H IC used in the Xserve G5 supports the PCI write combining feature. This feature allows sequential write transactions involving the Memory Write or Memory Write and Invalidate commands to be combined into a single PCI transaction. For memory write transactions to be combined, they must be sequential, ascending, and non-overlapping PCI addresses. Placing an eieio or sync command between the write commands prevents any write combining.

For more information, refer to PCI and PCI-X Expansion Slots .

Ethernet Controller

A separate Ethernet media access controller (MAC) and PHY support dual gigabit Ethernet. As a dedicated I/O channel on the dedicated PCI-X bus connected to the HyperTransport interface, it can operate at its full capacity without degrading the performance of other peripheral devices.

The MAC implements the link layer. It is integrated to a PHY interface that provides dual 10-BaseT, 100-BaseT, or 1000-BaseT operation over a standard twisted-pair interface. The operating speed of the link is automatically negotiated by the PHY and the bridge or router to which the Ethernet port is connected. For information about the port, see Ethernet Ports .

DMA Support

The K2 IC provides DB-DMA (descriptor-based direct memory access) support for the following I/O channels:

• Ultra ATA/100

• Communication slot interface

• I2S channel to the front panel display

• Serial ATA

• Firmware

The DB-DMA system provides a scatter-gather process based on memory-resident data structures that describe the data transfers. The DMA engine is enhanced to allow bursting of data files for improved performance.

Interrupt Support

The interrupt controller for the Xserve G5 system is an MPIC cell in the K2 IC. In addition to accepting K2 internal interrupt sources, the MPIC controller accepts internal interrupts from U3H and dedicated interrupt pins.

Internal PCI Bus

An internal 33-MHz, 64-bit PCI bus connects the K2 I/O controller to the boot ROM and the USB controller. The internal PCI bus offers no development opportunity.

Serial ATA Interface

Based on the Serial ATA 1.0 specification, Serial ATA (SATA) is a disk-interface technology that delivers up to 1.5 Gbps of performance to each independent drive on the Xserve G5. It provides a scalable, point-to-point connection that allows multiple ports to be aggregated into a single controller. Serial ATA uses a thin, point-to-point cable connection that enables easy routing within a system, avoiding master/slave, daisy-chaining, and termination issues and enabling better airflow within a system.

The K2 IC implements three Serial ATA revision one ports, each of which accommodates one independent internal hard drive.

For information about the drive bays, see Hard Disk Drives.

Serial Interface

The K2 IC implements an RS-232-compatible serial port for use with a terminal. See see Serial Port. You can use the RI input on the serial port connector to wake the Xserve G5 system from sleep mode.

Ultra DMA ATA/100 Interface

The K2 IC provides an Ultra DMA ATA/100 interface to support an optical drive. For information about optical drives, see SuperDrive (Optional) or Combo Drive .

FireWire Controllers

The K2 IC includes a FireWire controller that supports both IEEE 1394b (FireWire 800) with a maximum data rate of 800 Mbps (100 MBps) and IEEE 1394a (FireWire 400) with a maximum data rate of 400 Mbps (50 MBps). The IC is backwards-compatible with 1394a (FireWire 400). The K2 IC provides DMA (direct memory access) support for the FireWire interface.

Two physical layer (PHY) ICs connected to the U3H IC implement the electrical signaling protocol for the FireWire ports. The FireWire 400 port is located on the front panel; two FireWire 800 ports are located on the back panel.

While the PHYs are operating, they act as repeaters so that the FireWire bus remains connected. For more information, see FireWire Ports.

Power Controller

The power management controller in Xserve G5 is a microcontroller called the PMU99. It supports several modes of power management that provide significantly lower power consumption than previous systems.

Dual System Monitor ICs

The Xserve G5 hardware contains an IC that monitors system voltages and the operation of both fans in the Xserve G5 enclosure. Voltages monitored include 5 V main, 12 V main, 3.3 V trickle, 2.5 V sleep, logic Vcore and processor Vcore. The system monitor IC also contains a built-in temperature sensor that measures the hardware’s ambient temperature; a second sensor on the processor card measures local processor temperature. Software can access the system monitor IC through the second U3H IIC bus at port addresses 0x5A and 0x5C.

System Activity Lights

Two rows of eight lights indicate system activity. In a server with a single processor, the rows of system activity lights operate together; in a dual-processor server, the rows of lights operate independently to show each processor’s activity. In that case, CPU 0 is shown by the top row, CPU 1 by the bottom.

Device Identification

Each Xserve G5 boot ROM contains a unique device serial number. However, because the boot ROM is a flash EPROM device, it is possible to overwrite the serial number and lose it irrecoverably. As an alternative, software that needs to identify an individual Xserve G5 can access the local-mac-address property of its Ethernet node, which is set by Open Firmware at boot time. You can read this property using a tool such as IORegistry Explorer.