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Inside Macintosh: Processes
Chapter 1 - Introduction to Processes and Tasks / About Tasks

Task Creation

Many interrupt tasks are handled by system software and are transparent to your application. However, your application can use any of several facilities to install its own interrupt tasks that are executed not at regular points in the flow of its code but at intervals determined by hardware devices.

All of these managers need to maintain information about multiple interrupt tasks that might have been installed. To hold such information, the Operating System uses data structures known as operating-system queues. For more information on the structure of such queues, see the chapter "Queue Utilities" in Inside Macintosh: Operating System Utilities.

When an interrupt causes the microprocessor to suspend normal execution, the processor uses the stack to save the address of the next instruction and the processor's internal status. In this way, when the microprocessor completes execution of interrupt tasks, it can resume the current process where it left off.

After storing these values on the stack, the microprocessor executes an interrupt handler to deal with the interrupt. The addresses of all of the interrupt handlers, called interrupt vectors, are stored in a vector table in low memory. For example, if the interrupt is a vertical retrace interrupt, the microprocessor examines the value of the Vertical Retrace Manager's interrupt vector and executes the interrupt handler whose code starts at the address referenced by that value. The vertical retrace interrupt handler might then execute one or more vertical blanking tasks. When an interrupt task is executed, the interrupt is said to be serviced.

Each type of interrupt has an interrupt priority level, which defines how important it is that an interrupt be serviced. The microprocessor also maintains a processor priority that limits which interrupts will be serviced. When a device generates an interrupt whose interrupt priority level is higher than the processor priority level, the processor priority level is raised to the interrupt priority level, the interrupt is serviced, and the processor priority level is lowered to its previous level. When a device generates an interrupt whose interrupt priority level is lower than or equal to the processor priority level, the interrupt is ignored; interrupts of levels lower than the processor priority are said to be disabled when higher-level interrupts are executing. This scheme ensures that relatively important interrupts are not themselves interrupted by less important interrupts.

If you are writing a typical application, you do not need to worry about interrupts themselves or the low-level details associated with them. Your application installs interrupt tasks and ordinarily does not need to worry about the interrupts that cause them to execute. For more information on interrupts themselves, see the chapter "Device Manager" in Inside Macintosh: Devices and the chapter "Deferred Task Manager" in this book.

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© Apple Computer, Inc.
17 JUN 1996