Technical Q&A HW05

PCI Bus Performance with Memory Read and Memory Read Multiple Commands

Q: If I attempt to transfer a full cache line using the MemoryRead command, will I get lower performance than if I make the same transfer with the MemoryReadMultiple command?

A: Yes. If you use MemoryRead instead of MemoryReadLine or MemoryReadMultiple, you will be disconnected at eight-byte boundaries, because, just as with the writes, that is the size of a PowerPC single transaction. In the first implementation, a MemoryReadLine and MemoryReadMultiple are dealt with in the same way. There is no optimization for MemoryReadMultiple. However, you should use the MemoryReadMultiple transaction if that is what your PCI Master is doing, i.e., transferring multiple cache lines. Future bridges should take advantage of that. If you are doing a cache line read, or even close to a full cache line, you should do a MemoryReadLine.

Follow the PCI Specification's description of the different cycles. The general rule of thumb is:

• If the number of data phases is <= 2, use MemoryRead.
• If the number of data phases is > 2 and <= the cache line size, use MemoryReadLine.
• If the number of data phases > one cache line, use MemoryReadMultiple.

There are better guidelines than these in Rev. 2.1 of the PCI Specification. Although the PCI SIG hasn't officially released this revision of the specification, it should be available from your company's PCI SIG representative.