PowerPC Addressing Modes and Assembler Instructions

This chapter contains information specific to the PowerPC processor architecture.

PowerPC Registers and Addressing Modes

This section describes the conventions used to specify addressing modes and instruction mnemonics for the PowerPC series processor architecture. The instructions themselves are detailed in the next section, PowerPC Assembler Instructions.

Registers

Many instructions accept register names as operands. The available register names are listed in this section. These are the user registers:

Register

Description

r0-r31

General Purpose Registers

f0-f31

Floating-Point Registers

xer

Fixed-Point Exception Register

fpscr

Floating-Point Status and Control Register

cr

Condition Register

lr

Link Register

ctr

Count Register

v0–v31

Vector Registers (AltiVec specific)

For instructions that take either 0 or a general purpose register as an operand, r0 may not be used as either a zero or a register operand; the literal value 0 must be used instead.

These are the special registers

Registers

Description

sr0-sr15

Segment Registers

Operands and Addressing Modes

The PowerPC processor architecture has only one addressing mode for load and store instructions: register plus displacement. The general form for address operands is:

displacement(register)

If there is no displacement, the parentheses around the register name must still be used. For example, the first two of the following statements are legal, but the last isn't:

lwz   r12,4(r1)
lwz   r12,(r1)   ; same as displacement of 0
lwz   r12,r1     ; INCORRECT

To specify an arbitrary 32-bit address, two instructions must be used, since all instructions are 32 bits long and can't contain both an opcode and a full address. A pair of instructions used to load or store data at an address falls into one of a small set of idioms, using the assembler operators lo16(), hi16(), and ha16() to isolate the required portion of the 32-bit address expression. The idioms themselves are discussed below

  • lo16(expression) evaluates to the low (least significant) 16 bits of expression, with a relocation type of PPC_RELOC_LO16, PPC_RELOC_LO14, PPC_RELOC_LO16_SECTDIFF, or PPC_RELOC_LO14_SECTDIFF depending on the instruction and the expression it is used with.

  • hi16(expression) evaluates to the high (most significant) 16 bits of expression shifted right 16 bits, with a relocation type of PPC_RELOC_HI16 or PPC_RELOC_HI16_SECTDIFF depending on the expression it is used with.

  • ha16(expression) evaluates to the high (most significant) 16 bits of expression shifted right 16 bits, increased by one if bit 15 of expression is set (that is, if the value given by lo16(expression) is negative). This allows the address to be properly reconstituted when the low 16 bit quantity of expression is sign-extended by some operators. It has a relocation type of PPC_RELOC_HA16 or PPC_RELOC_HA16_SECTDIFF depending on the expression it is used with.

In specifying a 32-bit address, the desired result is that the 32-bit quantity be in a register. To do this, the high and low 16 bits of the address are entered separately with instructions suited to this task. Generally, the high 16 bits can be entered into a register with the addis (Add Immediate Shifted) instruction and the hi16() operator. For example, this instruction:

addis    r2,0,hi16(expr)

adds the high 16 bits of expr to 0, and enters the result into the high 16 bits of register 2. The instruction that immediately follows can then combine the low 16 bits with the high 16 bits in the register and perform whatever other operation it does (if any).

For example, to load the address of the global variable spot into general register 2, the instructions below would be used. The ori instruction doesn't sign-extend the displacement, so the high 16 bits of the address needn't be adjusted, and the hi16() assembler operator is used.

addis    r2,0,hi16(spot)   ; ori doesn't sign-extend
ori      r2,r2,lo16(spot)

In loading the data stored at spot the lwz operator is used, which does sign-extend the displacement, the adjusted high 16 bits must be given, with the ha16() assembler operator:

addis    r2,0,ha16(spot)   ; lwz sign-extends
lwz      r3,lo16(spot)(r2)

lwz treats the sign-extended low 16 bits as a displacement, adding it to the contents of register 2 to get a 32-bit address, and then loads the word at that address into register 3.

Extended Instruction Mnemonics & Operands

Branch Mnemonics

The PowerPC processor family supports a rich variety of extended mnemonics for its three conditional branch operators: bc, bclr, and bcctr. Normally, the condition and the nature of the branch are specified by numeric operands, but with the extended mnemonics, these numeric operands are determined by the assembler from the mnemonic used.

Conditional branches can alter the contents of the Count Register (ctr), and can take effect based on the resulting value in the Count Register, and on whether a specified condition is true or false. The first table below summarizes the extended mnemonics for branches that affect the Count Register, while the second summarizes additional mnemonics for branches on true and false conditions that don't affect the Count Register. The effect of the branch is given on the left. The first four columns of each table are for branches where the Link Register bit in the instruction is clear (not set); the remaining columns are for branches where the Link Register bit in the instruction is set. Each set of four columns gives mnemonics for relative and absolute branches, and for branches to the Link Register or the Count Register.

Branch Type

LR not set

LR set

bc

bca

bclr

bcctr

bcl

bcla

bclrl

bcctrl

Rel.

Abs.

to LR

to CTR

Rel.

Abs.

to LR

to CTR

unconditional

b

ba

blr

bctr

bl

bla

blrl

bctrl

if condition true

bt

bta

btlr

btctr

btl

btla

btlrl

btctrl

if condition false

bf

bfa

bflr

bfctr

bfl

bfla

bflrl

bfctrl

decrement CTR, branch if CTR non-zero

bdnz

bdnza

bdnzlr

bdnzl

bdnzla

bdnzlrl

Decrement CTR, branch if CTR non-zero and condition true

bdnzt

bdnzta

bdnztlr

bdnztl

bdnztla

bdnztlrl

Decrement CTR, branch if CTR non-zero and condition false

bdnzf

bdnzfa

bdnzflr

bdnzfl

bdnzfla

bdnzflrl

Decrement CTR, branch if CTR zero

bdz

bdza

bdzlr

bdzl

bdzla

bdzlrl

Decrement CTR, branch if CTR zero and condition true

bdzt

bdzta

bdztlr

bdztl

bdztla

bdztlrl

Decrement CTR, branch if CTR zero and condition false

bdzf

bdzfa

bdzflr

bdzfl

bdzfla

bdzflrl

The mnemonics in the table above encode specific values for the BO field of the non-extended operators. The BO field controls the effect on the Count Register and on what type of condition the branch is to be taken. The BI field, which controls the specific condition to consider, must still be given, as the first operand. The value of this operand indicates which field of the Condition Register to use, and which bit within that field to consider.

The Condition Register has 8 fields, numbered 0 to 7, each of which contains a bit for conditions less than, greater than, equal, and summary overflow or unordered. The numeric value for field n of the Condition Register is 4*n, and the numeric values for the conditions are 0, 1, 2, and 3, respectively. The following symbols may be used instead of numbers:

Symbol

Value

Meaning

lt

0

Less than

gt

1

Greater than

eq

2

Equal

so

3

Summary overflow

un

3

Unordered (after floating-point comparison)

cr0

0

Condition Register field 0

cr1

4

Condition Register field 1

cr2

8

Condition Register field 2

cr3

12

Condition Register field 3

cr4

16

Condition Register field 4

cr5

20

Condition Register field 5

cr6

24

Condition Register field 6

cr7

28

Condition Register field 7

For example, a branch if condition true for the condition greater than in Condition Register field 3 could be written in any of these ways:

bt    cr3+gt,target
bt    12+1,target
bt    13,target

Omitting the symbol for either the Condition Register field or the condition is permitted, as long as the result of the expression is a number from 0-31:

bt    gt,target     ; uses field 0
bt    cr3,target    ; branches on less than in field 3
bt    13,target     ; branches on less than in field 3

Another way to specify these conditions is to use the extended mnemonics in the second table, below. These mnemonics encode the actual condition on which to take a branch. The second and third letters of the mnemonic indicate that condition:

Code

Meaning

lt

Less than

le

Less than or equal

eq

Equal

ge

Greater than or equal

gt

Greater than

nl

Not less than

ne

Not equal

ng

Not greater than

so

Summary overflow

ns

Not summary overflow

uo

Unordered (after floating-point comparison)

nu

Not unordered (after floating-point comparison)

Some condition codes, such as le, are actually more compact codes for a false result on the opposite condition in the set of conditions given previously (for example, le is equivalent to if condition false on condition greater than).

By default, the extended mnemonics in the table below used Condition Register field 0. An optional first operand can be given to specify another field, in either numeric form or as a symbol of the form crn. For example:

bgt   target     ; branch if cr0 shows "greater than"
bgt   cr3,target ; branch if cr3 shows "greater than"

Branch Type

LR not set

LR set

bc

bca

bclr

bcctr

bcl

bcla

bclrl

bcctrl

Rel.

Abs.

to LR

to CTR

Rel.

Abs.

to LR

to CTR

less than

blt

blta

bltlr

bltctr

bltl

bltla

bltlrl

bltctrl

less than or equal

ble

blea

blelr

blectr

blel

blela

blelrl

blectrl

equal

beq

beqa

beqlr

beqctr

beql

beqla

beqlrl

beqctrl

greater than or equal

bge

bgea

bgelr

bgectr

bgel

bgela

bgerl

bgectrl

greater than

bgt

bgta

bgtlr

bgtctr

bgttl

bgla

bgtlrl

bgtctrl

not less than

bnl

bnla

bnllr

bnlctr

bnll

bnlla

bnllrl

bnlctrl

not equal

bne

bnea

bnelr

bnectr

bnel

bnela

bnelrl

bnectrl

not greater than

bng

bnga

bnglr

bngctr

bngl

bngla

bnglrl

bngctrl

summary overflow

bso

bsoa

bsolr

bsoctr

bsol

bsola

bsolrl

bsoctrl

not summary overflow

bns

bnsa

bnslr

bnsctr

bnsl

bnsla

bnslrl

bnsctrl

unordered

bun

buna

bunlr

bunctr

bunl

bunla

bunlrl

bunctrl

not unordered

bnu

bnua

bnulr

bnuctr

bnul

bnula

bnulrl

bnuctrl

Branch Prediction

PowerPC processors attempt to determine whether a conditional branch is likely to be taken or not. By default, they assume the following about conditional branches:

If the assembly language programmer knows the likely outcome of a conditional branch, a suffix can be added to the mnemonic that indicates which way the branch should be predicted to go: a ‘+’ instructs the processor to predict that the branch will be taken, while a ‘-’ instructs it to predict that the branch will not be taken. The branch prediction in for the 64-bit PowerPC AS architecture uses a different encoding for static branch prediction than the classic PowerPC architecture. This is encoded in the AT bits instead of the Y-bit of the conditional branch. The assembler takes ‘++’ and ‘--’ suffixes to encode branch prediction using the AT bits. The ‘+’ and ‘-’ suffixes encode the branch prediction using the Y-bit by default. The flag -static_branch_prediction_AT_bits changes this so that the ‘+’ and ‘-’ suffixes encode the AT bits. Where an operator allows a prediction suffix, a ‘±’ symbol appears after it in the table in PowerPC Assembler Instructions.

Use the jbsr pseudo instruction when you may not be able to reach the target of a branch and link instruction with a bl instruction. The jbsr instruction uses a sequence of code called a long branch stub which will always be able to reach the target.

jbsr  _foo,L1
     ...
L1:  lis  r12,hi16(_foo)    ; long branch stub
     ori  r12,r12,lo16(_foo)
     mtctr  r12
     bctr

The jbsr pseudo instruction assembles to a bl instruction targeted at L1. It also generates a PPC_RELOC_JBSR relocation entry for the symbol _foo. Then when the linker creates a non-relocatable output file it will change the target of the bl instruction to _foo if the bl instruction's displacement will reach. Else it will leave the bl instruction targeted at L1.

Trap Mnemonics

Like the branch-on-condition mnemonics above, the trap operator also has extended mnemonics which encode the numeric TO field as follows:

Code

Meaning

TO encoding

lt

Less than

16

le

Less than or equal

20

eq

Equal

4

ge

Greater than or equal

12

gt

Greater than

8

nl

Not less than

12

ne

Not equal

24

ng

Not greater than

20

llt

Logically less than

2

lle

Logically less than or equal

6

lge

Logically greater than or equal

5

lgt

Logically greater than

1

lnl

Logically not less than

5

lng

Logically not greater than

6

(none)

Unconditional

31

The condition is indicated from the third letter of the extended mnemonics in the table below:

Trap Type

64-bit comparison

32-bit-comparison

tdi

td

twi

tw

Immediate

Register

Immediate

Register

unconditional

trap

if less than

tdlti

tdlt

twlti

twlt

if less than or equal

tdlei

tdle

twlei

twle

if equal

tdeqi

tdeq

tweqi

tweq

if greater than or equal

tdgei

tdge

twgei

twge

if greater than

tdgti

tdgt

twgti

twgt

if not less than

tdnli

tdnl

twnli

twnl

if not equal

tdnei

tdne

twnei

twne

if not greater than

tdngi

tdng

twngi

twng

if logically less than

tdllti

tdllt

twllti

twllt

if logically less than or equal

tdllei

tdlle

twllei

twlle

if logically greater than or equal

tdlgei

tdlge

twlgei

twlge

if logically greater than

tdlgti

tdlgt

twlgti

twlgt

if logically not less than

tdlnli

tdlnl

twlnli

twlnl

if logically not greater than

tdlngi

tdlng

twlngi

twlng

PowerPC Assembler Instructions

Note the following points about the information contained in this section:

A

Operator

Operands

Operation Name

abs

RT,RA

Absolute (601 specific)

abs.

RT,RA

abso

RT,RA

abso.

RT,RA

add

RT,RA,RB

Add

add.

RT,RA,RB

addo

RT,RA,RB

addo.

RT,RA,RB

addc

RT,RA,RB

Add Carrying

addc.

RT,RA,RB

addco

RT,RA,RB

addco.

RT,RA,RB

adde

RT,RA,RB

Add Extended

adde.

RT,RA,RB

addeo

RT,RA,RB

addeo.

RT,RA,RB

addi

RT,RA,SI

Add Immediate

addic

RT,RA,SI

Add Immediate Carrying

addic.

RT,RA,SI

Add Immediate Carrying and Record

addis

RT,RA,UI

Add Immediate Shifted

addme

RT,RA

Add To Minus One Extended

addme.

RT,RA

addmeo

RT,RA

addmeo.

RT,RA

addze

RT,RA

Add To Zero Extended

addze.

RT,RA

addzeo

RT,RA

addzeo.

RT,RA

and

RA,RT,RB

AND

and.

RA,RT,RB

andc

RA,RT,RB

AND with Complement

andc.

RA,RT,RB

andi.

RA,RT,UI

AND Immediate

andis.

RA,RT,UI

AND Immediate Shifted

attn

UI

Support Processor Attention

B

Operator

Operands

Operation Name

b

target_addr

Branch

ba

target_addr

bl

target_addr

bla

target_addr

bc±

BO,BD,target_addr

Branch Conditional

bca±

BO,BD,target_addr

bcl±

BO,BD,target_addr

bcla±

BO,BD,target_addr

bclr±

BO,BD

Branch Conditional to Link Register

bclr

BO,BD, BH

bclr±

BO,BD, BH

bclrl±

BO,BD

bclrl±

BO,BD,BH

bcctr±

BO,BD

Branch Conditional to Count Register

bcctr±

BO,BD, BH

bcctrl±

BO,BD

bcctrl±

BO,BD,BH

bctr

Branch unconditionally to CTR

bctrl

bctrl

BH

bctr±

BO,BD

Equiv. to bcctr± BO,BD

bctrl±

BO,BD

Equiv. to bcctrl± BO,BD

bdnz±

target_addr

Decrement CTR, branch if CTR non-zero

bdnza±

target_addr

bdnzl±

target_addr

bdnzla±

target_addr

bdnzlr±

...to LR

bdnzlr±

BH

bdnzlrl±

bdnzlrl±

BH

bdnzf±

CRF+COND,target_addr

Decrement CTR, branch if CTR non-zero and condition false

bdnzfa±

CRF+COND,target_addr

bdnzfl±

CRF+COND,target_addr

bdnzfla±

CRF+COND,target_addr

bdnzflr±

CRF+COND

...to LR

bdnzflr±

CRF+COND, BH

.

bdnzflrl±

CRF+COND

bdnzflrl±

CRF+COND, BH

bdnzt±

CRF+COND,target_addr

Decrement CTR, branch if CTR non-zero and condition true

bdnzta±

CRF+COND,target_addr

bdnztl±

CRF+COND,target_addr

bdnztla±

CRF+COND,target_addr

bdnztlr±

CRF+COND

...to LR

bdnztlr±

CRF+COND,BH

bdnztlrl±

CRF+COND

bdnztlrl±

CRF+COND,BH

bdz±

target_addr

Decrement CTR, branch if CTR zero

bdza±

target_addr

bdzl±

target_addr

bdzla±

target_addr

bdzf±

CRF+COND,target_addr

Decrement CTR, branch if CTR zero and condition false

bdzfa±

CRF+COND,target_addr

bdzfl±

CRF+COND,target_addr

bdzfla±

CRF+COND,target_addr

bdzflr±

CRF+COND

...to LR

bdzflr±

CRF+COND,BH

.

bdzflrl±

CRF+COND

bdzflrl±

CRF+COND,BH

bdzlr±

bdzlr±

BH

bdzlrl±

bdzlrl±

BH

bdzt±

CRF+COND,target_addr

Decrement CTR, branch if CTR zero and condition false

bdzta±

CRF+COND,target_addr

bdztl±

CRF+COND,target_addr

bdztla±

CRF+COND,target_addr

bdztlr±

CRF+COND

...to LR

bdztlr±

CRF+COND,BH

bdztlrl±

CRF+COND

bdztlrl±

CRF+COND,BH

beq±

CRF,target_addr

Branch if equal

beq±

target_addr

beqa±

CRF,target_addr

beqa±

target_addr

beql±

CRF,target_addr

beql±

target_addr

beqla±

CRF,target_addr

beqla±

target_addr

beqctr±

CRF

...to CTR

beqctr±

CRF,BH

beqctr±

beqctrl±

CRF

beqctrl±

CRF,BH

beqctrl±

beqlr±

CRF

...to LR

beqlr±

CRF,BH

beqlr±

beqlrl±

CRF

beqlrl±

CRF,BH

beqlrl±

bf±

CRF+COND,target_addr

Branch if condition false

bfa±

CRF+COND,target_addr

bfl±

CRF+COND,target_addr

bfla±

CRF+COND,target_addr

bfctr±

CRF+COND

...to CTR

bfctr±

CRF+COND,BH

bfctrl±

CRF+COND

bfctrl±

CRF+COND,BH

bflr±

CRF+COND

...to LR

bflr±

CRF+COND,BH

bflrl±

CRF+COND

bflrl±

CRF+COND,BH

bge±

CRF,target_addr

Branch if greater than or equal

bge±

target_addr

bgea±

CRF,target_addr

bgea±

target_addr

bgel±

CRF,target_addr

bgel±

target_addr

bgela±

CRF,target_addr

bgela±

target_addr

bgectr±

CRF

...to CTR

bgectr±

CRF,BH

bgectr±

bgectrl±

CRF

bgectrl±

CRF,BH

bgectrl±

bgelr±

CRF

...to LR

bgelr±

CRF,BH

bgelr±

bgelrl±

CRF

bgelrl±

CRF,BH

bgelrl±

bgt±

CRF,target_addr

Branch if greater than

bgt±

target_addr

bgta±

CRF,target_addr

bgta±

target_addr

bgtl±

CRF,target_addr

bgtl±

target_addr

bgtla±

CRF,target_addr

bgtla±

target_addr

bgtctr±

CRF

...to CTR

bgtctr±

CRF,BH

bgtctr±

bgtctrl±

CRF

bgtctrl±

CRF,BH

bgtctrl±

bgtlr±

CRF

...to LR

bgtlr±

CRF,BH

bgtlr±

bgtlrl±

CRF

bgtlrl±

CRF,BH

bgtlrl±

ble±

CRF,target_addr

Branch if less than or equal

ble±

target_addr

blea±

CRF,target_addr

blea±

target_addr

blel±

CRF,target_addr

blel±

target_addr

blela+±

CRF,target_addr

blela±

target_addr

blectr±

CRF

...to CTR

blectr±

CRF,BH

blectr±

blectrl±

CRF

blectrl±

CRF,BH

blectrl±

blelr±

CRF

...to LR

blelr±

CRF,BH

blelr±

blelrl±

CRF

blelrl±

CRF,BH

blelrl±

blr

Branch unconditionally to LR

blr

BH

blrl

blrl

BH

blt±

CRF,target_addr

Branch if less than

blt±

target_addr

blta±

CRF,target_addr

blta±

target_addr

bltl±

CRF,target_addr

bltl±

target_addr

bltla±

CRF,target_addr

bltla±

target_addr

bltctr±

CRF

...to CTR

bltctr±

CRF,BH

bltctr±

bltctrl±

CRF

bltctrl±

CRF,BH

bltctrl±

bltlr±

CRF

...to LR

bltlr±

CRF,BH

bltlr±

bltlrl±

CRF

bltlrl±

CRF,BH

bltlrl±

bne±

CRF,target_addr

Branch if not equal

bne±

target_addr

bnea±

CRF,target_addr

bnea±

target_addr

bnel±

CRF,target_addr

bnel±

target_addr

bnela±

CRF,target_addr

bnela±

target_addr

bnectr±

CRF

...to CTR

bnectr±

CRF,BH

bnectr±

bnectrl±

CRF

bnectrl±

CRF,BH

bnectrl±

bnelr±

CRF

...to LR

bnelr±

CRF,BH

bnelr±

bnelrl±

CRF

bnelrl±

CRF,BH

bnelrl±

bng±

CRF,target_addr

Branch if not greater than

bng±

target_addr

bnga±

CRF,target_addr

bnga±

target_addr

bngl±

CRF,target_addr

bngl±

target_addr

bngla±

CRF,target_addr

bngla±

target_addr

bngctr±

CRF

...to CTR

bngctr±

CRF,BH

bngctr±

bngctrl±

CRF

bngctrl±

CRF,BH

bngctrl±

bnglr±

CRF

...to LR

bnglr±

CRF,BH

bnglr±

bnglrl±

CRF

bnglrl±

CRF,BH

bnglrl±

bnl±

CRF,target_addr

Branch if not less than

bnl±

target_addr

bnla±

CRF,target_addr

bnla±

target_addr

bnll±

CRF,target_addr

bnll±

target_addr

bnlla±

CRF,target_addr

bnlla±

target_addr

bnlctr±

CRF

...to CTR

bnlctr±

CRF,BH

bnlctr±

bnlctrl±

CRF

bnlctrl±

CRF,BH

bnlctrl±

bnllr±

CRF

...to LR

bnllr±

CRF,BH

bnllr±

bnllrl±

CRF

bnllrl±

CRF,BH

bnllrl±

bns±

CRF,target_addr

Branch if not summary overflow

bns±

target_addr

bnsa±

CRF,target_addr

bnsa±

target_addr

bnsl±

CRF,target_addr

bnsl±

target_addr

bnsla±

CRF,target_addr

bnsla±

target_addr

bnsctr±

CRF

...to CTR

bnsctr±

CRF,BH

bnsctr±

bnsctrl±

CRF

bnsctrl±

CRF,BH

bnsctrl±

bnslr±

CRF

...to LR

bnslr±

CRF,BH

bnslr±

bnslrl±

CRF

bnslrl±

CRF,BH

bnslrl±

bnu±

CRF,target_addr

Branch if not unordered

bnu±

target_addr

bnua±

CRF,target_addr

bnua±

target_addr

bnul±

CRF,target_addr

bnul±

target_addr

bnula±

CRF,target_addr

bnula±

target_addr

bnuctr±

CRF

...to CTR

bnuctr±

CRF,BH

bnuctr±

bnuctrl±

CRF

bnuctrl±

CRF,BH

bnuctrl±

bnulr±

CRF

...to LR

bnulr±

CRF,BH

bnulr±

bnulrl±

CRF

bnulrl±

CRF,BH

bnulrl±

bso±

CRF,target_addr

Branch if summary overflow

bso±

target_addr

bsoa±

CRF,target_addr

bsoa±

target_addr

bsol±

CRF,target_addr

bsol±

target_addr

bsola±

CRF,target_addr

bsola±

target_addr

bsoctr±

CRF

...to CTR

bsoctr±

CRF,BH

bsoctr±

bsoctrl±

CRF

bsoctrl±

CRF,BH

bsoctrl±

bsolr±

CRF

...to LR

bsolr±

CRF,BH

bsolr±

bsolrl±

CRF

bsolrl±

CRF,BH

bsolrl±

bt±

CRF+COND,target_addr

Branch if condition true

bta±

CRF+COND,target_addr

btl±

CRF+COND,target_addr

btla±

CRF+COND,target_addr

btctr±

CRF+COND

...to CTR

btctr±

CRF+COND,BH

btctrl±

CRF+COND

btlr±

CRF+COND

...to LR

btlr±

CRF+COND,BH

btlrl±

CRF+COND

btlrl±

CRF+COND,BH

bun±

CRF,target_addr

Branch if unordered

bun±

target_addr

buna±

CRF,target_addr

buna±

target_addr

bunl±

CRF,target_addr

bunl±

target_addr

bunla±

CRF,target_addr

bunla±

target_addr

bunctr±

CRF

...to CTR

bunctr±

CRF,BH

bunctr±

bunctrl±

CRF

bunctrl±

CRF,BH

bunctrl±

bunlr±

CRF

...to LR

bunlr±

CRF,BH

bunlr±

bunlrl±

CRF

bunlrl±

CRF,BH

bunlrl±

C

Operator

Operands

Operation Name

clcs

RD,RA

Cache Line Compute Size (601 specific)

clrldi

ra,rs,n

Macro: rldicl ra,rs,0,n

clrldi.

ra,rs,n

Macro: rldicl. ra,rs,0,n

clrlsldi

ra,rs,b,n

Macro: rldic ra,rs,n,b-n

clrlsldi.

ra,rs,b,n

Macro: rldic. ra,rs,n,b-n

clrlslwi

ra,rs,b,n

Macro: rlwinm ra,rs,n,b-n,31-n

clrlslwi.

ra,rs,b,n

Macro: rlwinm. ra,rs,n,b-n,31-n

clrlwi

ra,rs,n

Macro: rlwinm ra,rs,0,n,31

clrlwi.

ra,rs,n

Macro: rlwinm. ra,rs,0,n,31

clrrdi

ra,rs,n

Macro: rldicr ra,rs,0,63-n

clrrdi.

ra,rs,n

Macro: rldicr. ra,rs,0,63-n

clrrwi

ra,rs,n

Macro: rlwinm ra,rs,0,0,31-n

clrrwi.

ra,rs,n

Macro: rlwinm. ra,rs,0,0,31-n

cmp

BF,L,RA,RB

Compare

cmp

CRF,L,RA,RB

cmp

BF,RA,RB

Equiv to cmp BF,0,RA,RB

cmp

CRF,L,RA,RB

Equiv. to cmp CRF,0,RA,RB

cmpd

RA,RB

Equiv. to cmp 0,1,RA,RB

cmpd

BF,RA,RB

Equiv. to cmp BF,1,RA,RB

cmpd

CRF,RA,RB

Equiv. to cmp BF,1,RA,RB

cmpw

RA,RB

Equiv. to cmp 0,0,RA,RB

cmpw

BF,RA,RB

Equiv. to cmp BF,0,RA,RB

cmpw

CRF,RA,RB

Equiv. to cmp CRF,0,RA,RB

cmpi

BF,L,RA,SI

Compare Immediate

cmpi

CRF,L,RA,SI

cmpi

BF,RA,SI

Equiv. to cmpi BF,0,RA,SI

cmpi

CRF,RA,SI

Equiv. to cmpi CRF,0,RA,SI

cmpdi

RA,SI

Equiv. to cmpi 0,1,RA,SI

cmpdi

BF,RA,SI

Equiv. to cmp BF,1,RA,SI

cmpdi

CRF,RA,SI

Equiv. to cmpi CRF,1,RA,SI

cmpwi

RA,SI

Equiv. to cmpi 0,0,RA,SI

cmpwi

BF,RA,SI

Equiv. to cmpi BF,0,RA,SI

cmpwi

CRF,RA,SI

Equiv. to cmpi CRF,0,RA,SI

cmpl

BF,L,RA,RB

Compare Logical

cmpl

CRF,L,RA,RB

cmpl

BF,RA,RB

Equiv. to cmpl BF,0,RA,RB

cmpl

CRF,RA,RB

Equiv. to cmpl CRF,0,RA,RB

cmpld

RA,RB

Equiv. to cmpl 0,1,RA,RB

cmpld

BF,RA,RB

Equiv. to cmpl BF,1,RA,RB

cmpld

CRF,RA,RB

Equiv. to cmpl CRF,1,RA,RB

cmplw

RA,RB

Equiv. to cmpl 0,0,RA,RB

cmplw

BF,RA,RB

Equiv. to cmpl BF,0,RA,RB

cmplw

CRF,RA,RB

Equiv. to cmpl CRF,0,RA,RB

cmpli

BF,L,RA,UI

Compare Logical Immediate

cmpli

CRF,L,RA,UI

cmpli

BF,RA,UI

Equiv. to cmpli BF,0,RA,UI

cmpli

CRF,RA,UI

Equiv. to cmpli CRF,0,RA,UI

cmpldi

RA,UI

Equiv. to cmpi 0,1,RA,UI

cmpldi

BF,RA,UI

Equiv. to cmpi BF,1,RA,UI

cmpldi

CRF,RA,UI

Equiv. to cmpi CRF,1,RA,UI

cmplwi

BF,RA,UI

Equiv. to cmpi BF,0,RA,UI

cmplwi

CRF,RA,UI

Equiv. to cmpi CRF,0,RA,UI

cmplwi

RA,UI

Equiv. to cmpi CRF,0,RA,UI

cntlzd

RA,RT

Count Leading Zeros Doubleword

cntlzd.

RA,RT

cntlzw

RA,RT

Count Leading Zeros Word

cntlzw.

RA,RT

crand

BT,BA,BB

Condition Register AND

crandc

BT,BA,BB

Condition Register AND with Complement

creqv

BT,BA,BB

Condition Register Equivalent

crmove

BT,BA

Condition Register Move (Equiv. to cror BT,BA,BA)

crnand

BT,BA,BB

Condition Register NAND

crnor

BT,BA,BB

Condition Register NOR

crnot

BT,BA

Condition Register NOT (Equiv. to crnor BT,BA,BA)

cror

BT,BA,BB

Condition Register OR

crorc

BT,BA,BB

Condition Register OR with Complement

crxor

BT,BA,BB

Condition Register XOR

D

Operator

Operands

Operation Name

dcba

RA,RB

Data Cache Block Allocate

dcbf

RA,RB

Data Cache Block Flush

dcbi

RA,RB

Data Cache Block Invalidate

dcbst

RA,RB

Data Cache Block Store

dcbt

RA,RB

Data Cache Block Touch

dcbt

RA,RB,TH

Data Cache Block Touch X-form

dcbt128

RA,RB,TH

(same as above)

dcbtl

RA,RB

Data Cache Block Touch Line

dcbtl

RA,RB,TH

Data Cache Block Touch Line X-form

dcbtl128

RA,RB,TH

(same as above)

dcbtst

RA,RB

Data Cache Block Touch for Store

dcbz

RA,RB

Data Cache Block Set to Zero

dcbzl

RA,RB

Data Cache Block Set to Zero Line

dcbzl128

RA,RB

(same as above)

div

RT,RA,RB

Divide (601 specific)

div.

RT,RA,RB

divo

RT,RA,RB

divo.

RT,RA,RB

divd

RT,RA,RB

Divide Doubleword

divd.

RT,RA,RB

divdo

RT,RA,RB

divdo.

RT,RA,RB

divdu

RT,RA,RB

Divide Doubleword Unsigned

divdu.

RT,RA,RB

divduo

RT,RA,RB

divduo.

RT,RA,RB

divs

RT,RA,RB

Divide Short (601 specific)

divs.

RT,RA,RB

divso

RT,RA,RB

divso.

RT,RA,RB

divw

RT,RA,RB

Divide Word

divw.

RT,RA,RB

divwo

RT,RA,RB

divwo.

RT,RA,RB

divwu

RT,RA,RB

Divide Word Unsigned

divwu.

RT,RA,RB

divwuo

RT,RA,RB

divwuo.

RT,RA,RB

doz

RT,RA,RB

Difference or Zero (601 specific)

doz.

RT,RA,RB

dozo

RT,RA,RB

dozo.

RT,RA,RB

dozi

RT,RA,SI

Difference or Zero Immediate (601 specific)

dss

tag

Data Stream Stop (AltiVec specific)

dssall

Data Stream Stop All (AltiVec specific)

dst

RA,RB,tag

Data Stream Touch (AltiVec specific)

dstst

RA,RB,tag

Data Stream Touch for Store (AltiVec specific)

dststt

RA,RB,tag

Data Stream Touch for Store Transient (AltiVec specific)

dstt

RA,RB,tag

Data Stream Touch Transient (AltiVec specific)

E

Operator

Operands

Operation Name

eciwx

RT,RA,RB

External Control In Word Indexed

ecowx

RT,RA,RB

External Control Out Word Indexed

eieio

Enforce In-order Execution of I/O

eqv

RA,RT,RB

Equivalent

eqv.

RA,RT,RB

extldi

ra,rs,n,b

Macro: rldicr ra,rs,b,n-1

extldi.

ra,rs,n,b

Macro: rldicr. ra,rs,b,n-1

extlwi

ra,rs,n,b

Macro: rlwinm ra,rs,b,0,n-1

extlwi.

ra,rs,n,b

Macro: rlwinm. ra,rs,b,0,n-1

extrdi

ra,rs,n,b

Macro: rldicl ra,rs,b+n,64-n

extrdi.

ra,rs,n,b

Macro: rldicl. ra,rs,b+n,64-n

extrwi

ra,rs,n,b

Macro: rlwinm ra,rs,b+n,32-n,31

extrwi.

ra,rs,n,b

Macro: rlwinm. ra,rs,b+n,32-n,31

extsb

RA,RT

Extend Sign Byte

extsb.

RA,RT

extsh

RA,RT

Extend Sign Halfword

extsh.

RA,RT

extsw

RA,RT

Extend Sign Word

extsw.

RA,RT

F

Operator

Operands

Operation Name

fabs

FRT, FRB

Floating Absolute Value

fabs.

FRT, FRB

fadd

FRT,FRA,FRB

Floating Add

fadd.

FRT,FRA,FRB

fadds

FRT,FRA,FRB

fadds.

FRT,FRA,FRB

fcfid

FRT,FRB

Floating Convert From Integer Doubleword

fcfid.

FRT,FRB

fcmpo

BF,FRA,FRB

Floating Compare Ordered

fcmpo

CBF,FRA,FRB

fcmpu

BF,FRA,FRB

Floating Compare Unordered

fcmpu

CBF,FRA,FRB

fctid

FRT,FRB

Floating Convert to Integer Doubleword

fctid.

FRT,FRB

fctidz

FRT,FRB

Floating Convert to Integer Doubleword with Round toward Zero

fctidz.

FRT,FRB

fctiw

FRT,FRB

Floating Convert to Integer Word

fctiw.

FRT,FRB

fctiwz

FRT,FRB

Floating Convert to Integer Word with Round toward Zero

fctiwz.

FRT,FRB

fdiv

FRT,FRA,FRB

Floating Divide

fdiv.

FRT,FRA,FRB

fdivs

FRT,FRA,FRB

fdivs.

FRT,FRA,FRB

fmadd

FRT,FRA,FRC,FRB

Floating Multiply-Add [Single]

fmadd.

FRT,FRA,FRC,FRB

fmadds

FRT,FRA,FRC,FRB

fmadds.

FRT,FRA,FRC,FRB

fmr

FRT,FRB

Floating Move Register

fmr.

FRT,FRB

fmsub

FRT,FRA,FRC,FRB

Floating Multiply-Subtract

fmsub.

FRT,FRA,FRC,FRB

[Single]

fmsubs

FRT,FRA,FRC,FRB

fmsubs.

FRT,FRA,FRC,FRB

fmul

FRT,FRA,FRC

Floating Multiply

fmul.

FRT,FRA,FRC

fmuls

FRT,FRA,FRC

fmuls.

FRT,FRA,FRC

fnabs

FRT,FRB

Floating Negative Absolute Value

fnabs.

FRT,FRB

fneg

FRT,FRB

Floating Negate

fneg.

FRT,FRB

fnmadd

FRT,FRA,FRC,FRB

Floating Negative Multiply-Add [Single]

fnmadd.

FRT,FRA,FRC,FRB

fnmadds

FRT,FRA,FRC,FRB

fnmadds.

FRT,FRA,FRC,FRB

fnmsub

FRT,FRA,FRC,FRB

Floating Negative Multiply-Subtract [Single]

fnmsub.

FRT,FRA,FRC,FRB

fnmsubs

FRT,FRA,FRC,FRB

fnmsubs.

FRT,FRA,FRC,FRB

fres

FRT,FRB

Floating Reciprocal Estimate Single

fres.

FRT,FRB

frsp

FRT,FRB

Floating Round to Single-Precision

frsp.

FRT,FRB

frsqrte

FRT,FRB

Floating Reciprocal Square Root Estimate

frsqrte.

FRT,FRB

fsel

FRT,FRA,FRC,FRB

Floating Select

fsel.

FRT,FRA,FRC,FRB

fsqrt

FRT,FRB

Floating Square Root (Double-Precision)

fsqrt.

FRT,FRB

fsqrts

FRT,FRB

Floating Square Root Single

fsqrts.

FRT,FRB

fsub

FRT,FRA,FRB

Floating Subtract

fsub.

FRT,FRA,FRB

fsubs

FRT,FRA,FRB

fsubs.

FRT,FRA,FRB

I

Operator

Operands

Operation Name

icbi

RA,RB

Instruction Cache Block Invalidate

inslwi

ra,rs,n,b

Macro: rlwimi ra,rs,32-b,b,(b+n)-1

inslwi.

ra,rs,n,b

Macro: rlwimi. ra,rs,32-b,b,(b+n)-1

insrdi

ra,rs,n,b

Macro: rldimi ra,rs,64-(b+n),b

insrdi.

ra,rs,n,b

Macro: rldimi. ra,rs,64-(b+n),b

insrwi

ra,rs,n,b

Macro: rlwimi ra,rs,32-(b+n),b,(b+n)-1

insrwi.

ra,rs,n,b

Macro: rlwimi. ra,rs,32-(b+n),b,(b+n)-1

isync

Instruction Synchronize

J

Operator

Operands

Operation Name

jbsr

Lstub, Lbranch_island

Branch and Link (pseudo-instruction, see Branch Prediction for more)

jmp

Lstub, Lbranch_island

Branch (pseudo-instruction, see Branch Prediction for more)

L

Operator

Operands

Operation Name

la

RT,D(RA)

Load Address (Equiv to addi RT,RA,D)

lbz

RT,D(RA)

Load Byte and Zero

lbzu

RT,D(RA)

Load Byte and Zero with Update

lbzux

RT,RA,RB

Load Byte and Zero with Update Indexed

lbzx

RT,RA,RB

Load Byte and Zero Indexed

ld

RT,DS(RA)

Load Doubleword

ldarx

RT,RA,RB

Load Doubleword and Reserve Indexed

ldu

RT,DS(RA)

Load Doubleword with Update

ldux

RT,RA,RB

Load Doubleword with Update Indexed

ldx

RT,RA,RB

Load Doubleword Indexed

lfd

FRT,D(RA)

Load Floating-Point Double

lfdu

FRT,D(RA)

Load Floating-Point Double with Update

lfdux

FRT,RA,RB

Load Floating-Point Double with Update Indexed

lfdx

FRT,RA,RB

Load Floating-Point Double Indexed

lfs

FRT,D(RA)

Load Floating-Point Single

lfsu

FRT,D(RA)

Load Floating-Point Single with Update

lfsux

FRT,RA,RB

Load Floating-Point Single with Update Indexed

lfsx

FRT,RA,RB

Load Floating-Point Single Indexed

lha

RT,D(RA)

Load Halfword Algebraic

lhau

RT,D(RA)

Load Halfword Algebraic with Update

lhaux

RT,RA,RB

Load Halfword Algebraic with Update Indexed

lhax

RT,RA,RB

Load Halfword Algebraic Indexed

lhbrx

RT,RA,RB

Load Halfword Byte-Reverse Indexed

lhz

RT,D(RA)

Load Halfword and Zero

lhzu

RT,D(RA)

Load Halfword and Zero with Update

lhzux

RT,RA,RB

Load Halfword and Zero with Update Indexed

lhzx

RT,RA,RB

Load Halfword and Zero Indexed

li

Rx,value

Load Immediate

lis

Rx,value

lmw

RT,D(RA)

Load Multiple Word

lscbx

RT,RA,RB

Load String and Compare Byte Indexed (601 specific)

lscbx.

RT,RA,RB

lswi

RT,RA,NB

Load String Word Immediate

lswx

RT,RA,RB

Load String Word Indexed

lvebx

VT,RA,RB

Load Vector Element Byte Indexed (AltiVec specific)

lvehx

VT,RA,RB

Load Vector Element Halfword Indexed (AltiVec specific)

lvewx

VT,RA,RB

Load Vector Element Word Indexed (AltiVec specific)

lvsl

VT,RA,RB

Load Vector for Shift Left (AltiVec specific)

lvsr

VT,RA,RB

Load Vector for Shift Right (AltiVec specific)

lvx

VT,RA,RB

Load Vector Indexed (AltiVec specific)

lvxl

VT,RA,RB

Load Vector Indexed LRU (AltiVec specific)

lwa

RT,DS(RA)

Load Word Algebraic

lwarx

RT,RA,RB

Load Word and Reserve Indexed

lwaux

RT,RA,RB

Load Word Algebraic with Update Indexed

lwax

RT,RA,RB

Load Word Algebraic Indexed

lwbrx

RT,RA,RB

Load Word Byte-Reverse Indexed

lwsync

Light-Weight Sync Operation

lwz

RT,D(RA)

Load Word and Zero

lwzu

RT,D(RA)

Load Word and Zero with Update

lwzux

RT,RA,RB

Load Word and Zero with Update Indexed

lwzx

RT,RA,RB

Load Word and Zero Indexed

M

Operator

Operands

Operation Name

maskg

RA,RS,RB

Mask Generate (601 specific)

maskg.

RA,RS,RB

maskir

RA,RS,RB

Mask Insert From Register (601 specific)

maskir.

RA,RS,RB

mcrf

CRF,CRF

Move Condition Register Field

mcrf

BF,BFA

mcrfs

BF,BFA

Move to Condition Register from FPSCR

mcrfs

CRF,BFA

mcrxr

BF

Move to Condition Register from XER

mcrxr

CRF

mfcr

RT

Move From Condition Register

mfcr

RT,FXM

mfctr

RT

Move From Count Register

mffs

FRT

Move From FPSCR

mffs.

FRT

mfmsr

RT

Move From Machine State Register

mfspr

RT,SPR

Move From Special Purpose Register

mfxer

Rx

Fixed-Point Exception Register (equiv. to mfspr 1,Rx)

mflr

Rx

Link Register (equiv. to mfspr 8,Rx)

mfctr

Rx

Count Register (equiv. to mfspr 8,Rx)

mfdsisr

Rx

Data Storage Interrupt Status Register (macro)

mfdar

Rx

Data Address Register (macro)

mfdec

Rx

Decrementer (macro)

mfear

Rx

Move from External Address (Equiv. to mfspr 282, Rx)

mfsdr1

Rx

Storage Description Register 1 (macro)

mfsrr0

Rx

Save/Restore Register 0 (macro)

mfsrr1

Rx

Save/Restore Register 1 (macro)

mfsprg

n,Rx

Special Purpose Register n (macro)

mfasr

Rx

Address Space Register (macro)

mfmq

Rx

Move from MQ Register (601 Only) (Equiv to mfspr 0,Rx)

mfrtcd

Rx

Real Time Clock Divisor (macro)

mfrtcl

Rx

Move from Real Time Clock Lower (601 Only) (Equiv. to mfspr 5, Rx)

mfrtcu

Rx

Move from Real Time Clock Upper (601 Only) (Equiv. to mfspr 4, Rx)

mfrtci

Rx

Real Time Clock Increment (macro)

mfpvr

Rx

Processor Version Register (macro)

mfibatu

n,Rx

IBAT Register n, Upper (macro)

mfibatl

n,Rx

IBAT Register n, Lower (macro)

mfdbatu

n,Rx

DBAT Register n, Upper (macro)

mfdbatl

n,Rx

DBAT Register n, Lower (macro)

mfsr

RT,SR

Move From Segment Register

mfsrin

RT,RB

Move From Segment Register Indirect

mftb

RT

Move from Time Base

mftb

RT,TBR

mftbu

RT

Move from Time Base Upper

mfvscr

VT

Move From Vector Status and Control Register (AltiVec specific)

mr

Rx,Ry

Move Register

mr.

Rx,Ry

mtcrf

FXM,RT

Move to Condition Register Fields

mtfsb0

BT

Move to FPSCR Bit 0

mtfsb0.

BT

mtfsb1

BT

Move to FPSCR Bit 1

mtfsb1.

BT

mtfsf

FLM,FRB

Move to FPSCR Fields

mtfsf.

FLM,FRB

mtfsfi

BF,U

Move to FPSCR Field Immediate

mtfsfi.

BF,U

mtfs

Rx

Equiv. to mtfsf 0xFF,Rx

mtfs.

Rx

Equiv. to mtfsf. OxFF, Rx

mtmsr

RT

Move to Machine State Register

mtmsrd

RA

mtmsrd

RA,L

mtspr

SPR,RT

Move To Special Purpose Register

mtxer

Rx

Fixed-Point Exception Register (equiv. to mtspr 1,Rx)

mtlr

Rx

Link Register (equiv. to mtspr 8,Rx)

mtctr

Rx

Count Register (equiv. to mtspr 8,Rx)

mtdsisr

Rx

Data Storage Interrupt Status Register (macro)

mtdar

Rx

Data Address Register (macro)

mtdec

Rx

Decrementer (macro)

mtear

Rx

Move to External Address Register (Equiv. to mtspr 282,Rx)

mtsdr1

Rx

Storage Description Register 1 (macro)

mtsrr0

Rx

Save/Restore Register 0 (macro)

mtsrr1

Rx

Save/Restore Register 1 (macro)

mtsprg

n,Rx

Special Purpose Register n (macro)

mtasr

Rx

Address Space Register (macro)

mtmq

Rx

Move to MQ Register (601 Only) (Equiv. to mtspr 0,Rx)

mtrtcd

Rx

Real Time Clock Divisor (macro)

mtrtcl

Rx

Move to Real Time Clock Lower (601 Only) (Equiv. to mtspr 21,Rx)

mtrtcu

Rx

Move to Real Time Clock Upper (601 Only) (Equiv. to mtspr 20,Rx)

mtrtci

Rx

Real Time Clock Increment (macro)

mtibatu

n,Rx

IBAT Register n, Upper (macro)

mtibatl

n,Rx

IBAT Register n, Lower (macro)

mtdbatu

n,Rx

DBAT Register n, Upper (macro)

mtdbatl

n,Rx

DBAT Register n, Lower (macro)

mtsr

SR,RT

Move to Segment Register

mtsrin

RT,RB

Move to Segment Register Indirect

mttbu

RB

Move to Time Base Upper (Equiv. to mtspr 285,RB)

mttrbl

RB

Move to Time Base Lower (Equiv. to mtspr 284,RB)

mtvscr

VB

Move To Vector Status and Control Register (AltiVec specific)

mul

RT,RA,RB

Multiply (601 specific)

mul.

RT,RA,RB

mulo

RT,RA,RB

mulo.

RT,RA,RB

mulhd

RT,RA,RB

Multiply High Doubleword

mulhd.

RT,RA,RB

mulhdu

RT,RA,RB

Multiply High Doubleword Unsigned

mulhdu.

RT,RA,RB

mulhw

RT,RA,RB

Multiply High Word

mulhw.

RT,RA,RB

mulhwu

RT,RA,RB

Multiply High Word Unsigned

mulhwu.

RT,RA,RB

mulld

RT,RA,RB

Multiply Low Doubleword

mulld.

RT,RA,RB

mulldo

RT,RA,RB

mulldo.

RT,RA,RB

mullw

RT,RA,RB

Multiply Low

mullw.

RT,RA,RB

mullwo

RT,RA,RB

mullwo.

RT,RA,RB

mulli

RT,RA,SI

Multiply Low Immediate

N

Operator

Operands

Operation Name

nabs

RT,RA

Negative Absolute (601 specific)

nabs.

RT,RA

nabso

RT,RA

nabso.

RT,RA

nand

RA,RT,RB

NAND

nand.

RA,RT,RB

neg

RT,RA

Negate

neg.

RT,RA

nego

RT,RA

nego.

RT,RA

nop

No-op

nor

RA,RT,RB

Nor

nor.

RA,RT,RB

not

RA,RT

Not

not.

RA,RT

O

Operator

Operands

Operation Name

or

RA,RT,RB

OR

or.

RA,RT,RB

orc

RA,RT,RB

OR with Complement

orc.

RA,RT,RB

ori

RA,RT,UI

OR Immediate

oris

RA,RT,UI

OR Immediate Shifted

P

Operator

Operands

Operation Name

ptesync

Page Table Entry Synchronize

R

Operator

Operands

Operation Name

rfi

Return From Interrupt

rfid

Return From Interrupt Doubleword

rldcl

RA,RS,RB,mb

Rotate Left Doubleword then Clear Left

rldcl.

RA,RS,RB,mb

rldcr

RA,RS,RB,mb

Rotate Left Doubleword then Clear Right

rldcr.

RA,RS,RB,mb

rldic

RA,RS,sh,mb

Rotate Left Doubleword Immediate then Clear

rldic.

RA,RS,sh,mb

rldicl

RA,RS,sh,mb

Rotate Left Doubleword Immediate then Clear Left

rldicl.

RA,RS,sh,mb

rldicr

RA,RS,sh,mb

Rotate Left Doubleword Immediate then Clear

rldicr.

RA,RS,sh,mb

Right

rldimi

RA,RS,sh,mb

Rotate Left Doubleword then Mask Insert

rldimi.

RA,RS,sh,mb

rlmi

RA,RS,RB,MB,ME

Rotate Left then Mask Insert (601 specific)

rlmi.

RA,RS,RB,MB,ME

rlmi

RA,RS,RB,BM

Rotate Left then Mask Insert (601 specific)

rlmi.

RA,RS,RB,BM

rlwimi

RA,RS,SH,MB,ME

Rotate Left Word Immediate then Mask Insert

rlwimi.

RA,RS,SH,MB,ME

rlwimi

RA,RS,SH,BM

Rotate Left Word Immediate then Mask Insert

rlwimi.

RA,RS,SH,BM

rlwinm

RA,RS,SH,MB,ME

Rotate Left Word Immediate then AND with Mask

rlwinm.

RA,RS,SH,MB,ME

rlwinm

RA,RS,SH,BM

Rotate Left Word Immediate then AND with Mask

rlwinm.

RA,RS,SH,BM

rlwnm

RA,RS,RB,MB,ME

Rotate Left Word then AND with Mask

rlwnm.

RA,RS,RB,MB,ME

rlwnm

RA,RS,SH,BM

Rotate Left Word then AND with Mask

rlwnm.

RA,RS,SH,BM

rotld

ra,rs,rb

Macro: rldicl ra,rs,rb,0

rotld.

ra,rs,rb

Macro: rldicl. ra,rs,rb,0

rotldi

ra,rs,n

Macro: rldicl ra,rs,n,0

rotldi.

ra,rs,n

Macro: rldicl. ra,rs,n,0

rotlw

ra,rs,rb

Macro: rlwnm ra,rs,rb,0,31

rotlw.

ra,rs,rb

Macro: rlwnm. ra,rs,rb,0,31

rotlwi

ra,rs,n

Macro: rlwinm ra,rs,n,0,31

rotlwi.

ra,rs,n

Macro: rlwinm. ra,rs,n,0,31

rotrdi

ra,rs,n

Macro: rldicl ra,rs,64-n,0

rotrdi.

ra,rs,n

Macro: rldicl. ra,rs,64-n,0

rotrwi

ra,rs,n

Macro: rlwinm ra,rs,32-n,0,31

rotrwi.

ra,rs,n

Macro: rlwinm. ra,rs,32-n,0,31

rrib

RA,RS,RB

Rotate Right and Insert Bit (601 specific)

rrib.

RA,RS,RB

S

Operator

Operands

Operation Name

sc

System Call

slbia

Segment Lookaside Buffer Invalidate All

slbie

RB

Segment Lookaside Buffer Invalidate Entry

slbmfee

RS,RB

SLB Move From Entry ESID

slbmfev

RS,RB

SLB Move From Entry VSID

slbmte

RS,RB

SLB Move To Entry

sld

RA,RS,RB

Shift Left Doubleword

sld.

RA,RS,RB

sldi

ra,rs,n

Macro: rldicr ra,rs,n,63-n

sldi.

ra,rs,n

Macro: rldicr. ra,rs,n,63-n

slwi

ra,rs,n

Macro: rlwinm ra,rs,n,0,31-n

slwi.

ra,rs,n

Macro: rlwinm. ra,rs,n,0,31-n

sle

RA,RS,RB

Shift Left Extended (601 specific)

sle.

RA,RS,RB

sleq

RA,RS,RB

Shift Left Extended with MQ (601 specific)

sleq.

RA,RS,RB

sliq

RA,RS,SH

Shift Left Immediate with MQ (601 specific)

sliq.

RA,RS,SH

slliq

RA,RS,SH

Shift Left Long Immediate with MQ (601 specific)

slliq.

RA,RS,SH

sllq

RA,RS,RB

Shift Left Long with MQ (601 specific)

sllq.

RA,RS,RB

slq

RA,RS,RB

Shift Left with MQ (601 specific)

slq.

RA,RS,RB

slw

RA,RS,RB

Shift Left Word

slw.

RA,RS,RB

srad

RA,RS,RB

Shift Right Algebraic Doubleword

srad.

RA,RS,RB

sradi

RA,RS,sh

Shift Right Algebraic Doubleword Immediate

sradi.

RA,RS,sh

sraiq

RA,RS,SH

Shift Right Algebraic Immediate with MQ (601 specific)

sraiq.

RA,RS,SH

sraq

RA,RS,RB

Shift Right Algebraic with MQ (601 specific)

sraq.

RA,RS,RB

sraw

RA,RS,RB

Shift Right Algebraic Word

sraw.

RA,RS,RB

srawi

RA,RS,SH

Shift Right Algebraic Word Immediate

srawi.

RA,RS,SH

srd

RA,RS,RB

Shift Right Doubleword

srd.

RA,RS,RB

srdi

ra,rs,n

Macro: rldicl ra,rs,64-n,n

srdi.

ra,rs,n

Macro: rldicl. ra,rs,64-n,n

srwi

ra,rs,n

Macro: rlwinm ra,rs,32-n,n,31

srwi.

ra,rs,n

Macro: rlwinm. ra,rs,32-n,n,31

sre

RA,RS,RB

Shift Right Extended (601 specific)

sre.

RA,RS,RB

srea

RA,RS,RB

Shift Right Extended Algebraic (601 specific)

srea.

RA,RS,RB

sreq

RA,RS,RB

Shift Right Extended with MQ (601 specific)

sreq.

RA,RS,RB

sriq

RA,RS,SH

Shift Right Immediate with MQ (601 specific)

sriq.

RA,RS,SH

srliq

RA,RS,SH

Shift Right Long Immediate with MQ (601 specific)

srliq.

RA,RS,SH

srlq

RA,RS,RB

Shift Right Long with MQ (601 specific)

srlq.

RA,RS,RB

srq

RA,RS,RB

Shift Right with MQ (601 specific)

srq.

RA,RS,RB

srw

RA,RS,RB

Shift Right Word

srw.

RA,RS,RB

stb

RT,D(RA)

Store Byte

stbu

RT,D(RA)

Store Byte with Update

stbux

RT,RA,RB

Store Byte with Update Indexed

stbx

RT,RA,RB

Store Byte Indexed

std

RT,DS(RA)

Store Doubleword

stdcx.

RT,RA,RB

Store Doubleword Conditional Indexed

stdu

RT,DS(RA)

Store Doubleword with Update

stdux

RT,RA,RB

Store Doubleword with Update Indexed

stdx

RT,RA,RB

Store Doubleword Indexed

stfd

FRT,D(RA)

Store Floating-Point Double

stfdu

FRT,D(RA)

Store Floating-Point Double with Update

stfdux

FRT,RA,RB

Store Floating-Point Double with Update Indexed

stfdx

FRT,RA,RB

Store Floating-Point Double Indexed

stfiwx

FRT,RA,RB

Store Floating-Point as Integer Word Indexed

stfs

FRT,D(RA)

Store Floating-Point Single

stfsu

FRT,D(RA)

Store Floating-Point Single with Update

stfsux

FRT,RA,RB

Store Floating-Point Single with Update Indexed

stfsx

FRT,RA,RB

Store Floating-Point Single Indexed

sth

RT,D(RA)

Store Halfword

sthbrx

RT,RA,RB

Store Halfword Byte-Reverse Indexed

sthu

RT,D(RA)

Store Halfword with Update

sthux

RT,RA,RB

Store Halfword with Update Indexed

sthx

RT,RA,RB

Store Halfword Indexed

stvebx

VS,RA,RB

Store Vector Element Byte Indexed (AltiVec specific)

stvehx

VS,RA,RB

Store Vector Element Halfword Indexed (AltiVec specific)

stvewx

VS,RA,RB

Store Vector Element Word Indexed (AltiVec specific)

stvx

VS,RA,RB

Store Vector Indexed (AltiVec specific)

stvxl

VS,RA,RB

Store Vector Indexed LRU (AltiVec specific)

stmw

RT,D(RA)

Store Multiple Word

stswi

RT,RA,NB

Store String Word Immediate

stswx

RT,RA,RB

Store String Word Indexed

stw

RT,D(RA)

Store Word

stwbrx

RT,RA,RB

Store Word Byte-Reverse Indexed

stwcx.

RT,RA,RB

Store Word Conditional Indexed

stwu

RT,D(RA)

Store Word with Update

stwux

RT,RA,RB

Store Word with Update Indexed

stwx

RT,RA,RB

Store Word Indexed

sub

RT,RB,RA

Equiv. to subf RT,RA,RB

sub.

RT,RB,RA

Equiv. to subf. RT,RA,RB

subo

RT,RB,RA

Equiv. to subfo RT,RA,RB

subo.

RT,RB,RA

Equiv. to subfo. RT,RA,RB

subc

RT,RB,RA

Equiv. to subfc RT,RA,RB

subc.

RT,RB,RA

Equiv. to subfc. RT,RA,RB

subco

RT,RB,RA

Equiv. to subfco RT,RA,RB

subco.

RT,RB,RA

Equiv. to subfco. RT,RA,RB

subf

RT,RA,RB

Subtract From

subf.

RT,RA,RB

subfo

RT,RA,RB

subfo.

RT,RA,RB

subfc

RT,RA,RB

Subtract From Carrying

subfc.

RT,RA,RB

subfco

RT,RA,RB

subfco.

RT,RA,RB

subfe

RT,RA,RB

Subtract From Extended

subfe.

RT,RA,RB

subfeo

RT,RA,RB

subfeo.

RT,RA,RB

subfic

RT,RA,SI

Subtract From Immediate Carrying

subfme

RT,RA

Subtract From Minus One Extended

subfme.

RT,RA

subfmeo

RT,RA

subfmeo.

RT,RA

subfze

RT,RA

Subtract From Zero Extended

subfze.

RT,RA

subfzeo

RT,RA

subfzeo.

RT,RA

subi

Rx,Ry,value

Equiv. to addi Rx,Ry,-value

subic

Rx,Ry,value

Equiv. to addic Rx,Ry,-value

subic.

Rx,Ry,value

Equiv. to addic. Rx,Ry,-value

subis

Rx,Ry,value

Equiv. to addis Rx,Ry,-value

sync

Synchronize

sync

L

T

Operator

Operands

Operation Name

td

TO,RA,RB

Trap Doubleword

tdeq

RA,RB

if equal

tdne

RA,RB

if not equal

tdgt

RA,RB

if greater than

tdge

RA,RB

if greater than or equal

tdng

RA,RB

if not greater than

tdlt

RA,RB

if less than

tdle

RA,RB

if less than or equal

tdnl

RA,RB

if not less than

tdlgt

RA,RB

if logically greater than

tdlge

RA,RB

if logically greater than or equal

tdlng

RA,RB

if logically not greater than

tdllt

RA,RB

if logically less than

tdlle

RA,RB

if logically less than or equal

tdlnl

RA,RB

if logically not less than

tdi

TO,RA,SI

Trap Doubleword Immediate

tdeqi

RA,SI

if equal

tdnei

RA,SI

if not equal

tdgti

RA,SI

if greater than

tdgei

RA,SI

if greater than or equal

tdngi

RA,SI

if not greater than

tdlti

RA,SI

if less than

tdlei

RA,SI

if less than or equal

tdnli

RA,SI

if not less than

tdlgti

RA,SI

if logically greater than

tdlgei

RA,SI

if logically greater than or equal

tdlngi

RA,SI

if logically not greater than

tdllti

RA,SI

if logically less than

tdllei

RA,SI

if logically less than or equal

tdlnli

RA,SI

if logically not less than

tlbia

Translation Lookaside Buffer Invalidate All

tlbie

RB

Translation Lookaside Buffer Invalidate Entry

tlbie

RB,L

tlbiel

RB

Translation Lookaside Buffer Invalidate Entry Local

tlbld

RB

Load Data TLB Entry (603 specific)

tlbli

RB

Load Instruction TLB Entry (603 specific)

tlbsync

TLB Synchronize

trap

Trap Unconditionally

tw

TO,RA,RB

Trap Word

tweq

RA,RB

if equal

twne

RA,RB

if not equal

twgt

RA,RB

if greater than

twge

RA,RB

if greater than or equal

twng

RA,RB

if not greater than

twlt

RA,RB

if less than

twle

RA,RB

if less than or equal

twnl

RA,RB

if not less than

twlgt

RA,RB

if logically greater than

twlge

RA,RB

if logically greater than or equal

twlng

RA,RB

if logically not greater than

twllt

RA,RB

if logically less than

twlle

RA,RB

if logically less than or equal

twlnl

RA,RB

if logically not less than

twi

TO,RA,SI

Trap Word Immediate

tweqi

RA,RB

if equal

twnei

RA,RB

if not equal

twgti

RA,RB

if greater than

twgei

RA,RB

if greater than or equal

twngi

RA,RB

if not greater than

twlti

RA,RB

if less than

twlei

RA,RB

if less than or equal

twnli

RA,RB

if not less than

twlgti

RA,RB

if logically greater than

twlgei

RA,RB

if logically greater than or equal

twlngi

RA,RB

if logically not greater than

twllti

RA,RB

if logically less than

twllei

RA,RB

if logically less than or equal

twlnli

RA,RB

if logically not less than

V

Operator

Operands

Operation Name

vaddcuw

VT,VA,VB

Vector Add Carry-out Unsigned Word (AltiVec specific)

vaddfp

VT,VA,VB

Vector Add Float (AltiVec specific)

vaddsbs

VT,VA,VB

Vector Add Signed Byte Saturate (AltiVec specific)

vaddshs

VT,VA,VB

Vector Add Signed Halfword Saturate (AltiVec specific)

vaddsws

VT,VA,VB

Vector Add Signed Word Saturate (AltiVec specific)

vaddubm

VT,VA,VB

Vector Add Unsigned Byte Modulo (AltiVec specific)

vaddubs

VT,VA,VB

Vector Add Unsigned Byte Saturate (AltiVec specific)

vadduhm

VT,VA,VB

Vector Add Unsigned Halfword Modulo (AltiVec specific)

vadduhs

VT,VA,VB

Vector Add Unsigned Halfword Saturate (AltiVec specific)

vadduwm

VT,VA,VB

Vector Add Unsigned Word Modulo (AltiVec specific)

vadduws

VT,VA,VB

Vector Add Unsigned Word Saturate (AltiVec specific)

vand

VT,VA,VB

Vector Logical AND (AltiVec specific)

vandc

VT,VA,VB

Vector Logical AND with Complement (AltiVec specific)

vmaddfp

VT,VA,VC,VB

Vector Multiply-Add Float (AltiVec specific)

vavgsb

VT,VA,VB

Vector Average Signed Byte (AltiVec specific)

vavgsh

VT,VA,VB

Vector Average Signed Halfword (AltiVec specific)

vavgsw

VT,VA,VB

Vector Average Signed Word (AltiVec specific)

vavgub

VT,VA,VB

Vector Average Unsigned Byte (AltiVec specific)

vavguh

VT,VA,VB

Vector Average Unsigned Halfword (AltiVec specific)

vavguw

VT,VA,VB

Vector Average Unsigned Word (AltiVec specific)

vcfsx

VT,VB,UIM

Vector Convert From Signed fiXed-point word (AltiVec specific)

vcfux

VT,VB,UIM

Vector Convert From Unsigned fiXed-point word (AltiVec specific)

vcmpbfp

VT,VA,VB

Vector Compare Bounds Float [Record] (AltiVec specific)

vcmpbfp.

VT,VA,VB

vcmpeqfp

VT,VA,VB

Vector Compare Equal-To Float [Record] (AltiVec specific)

vcmpeqfp.

VT,VA,VB

vcmpequb

VT,VA,VB

Vector Compare Equal-To Unsigned Byte [Record] (AltiVec specific)

vcmpequb.

VT,VA,VB

vcmpequh

VT,VA,VB

Vector Compare Equal-To Unsigned Halfword [Record] (AltiVec specific)

vcmpequh.

VT,VA,VB

vcmpequw

VT,VA,VB

Vector Compare Equal-To Unsigned Word [Record] (AltiVec specific)

vcmpequw.

VT,VA,VB

vcmpgefp

VT,VA,VB

Vector Compare Greater-Than-or-Equal-To Float [Record] (AltiVec specific)

vcmpgefp.

VT,VA,VB

vcmpgtfp

VT,VA,VB

Vector Compare Greater-Than Float [Record] (AltiVec specific)

vcmpgtfp.

VT,VA,VB

vcmpgtsb

VT,VA,VB

Vector Compare Greater-Than Signed Byte [Record] (AltiVec specific)

vcmpgtsb.

VT,VA,VB

vcmpgtsh

VT,VA,VB

Vector Compare Greater-Than Signed Halfword [Record] (AltiVec specific)

vcmpgtsh.

VT,VA,VB

vcmpgtsw

VT,VA,VB

Vector Compare Greater-Than Signed Word [Record] (AltiVec specific)

vcmpgtsw.

VT,VA,VB

vcmpgtub

VT,VA,VB

Vector Compare Greater-Than Unsigned Byte [Record] (AltiVec specific)

vcmpgtub.

VT,VA,VB

vcmpgtuh

VT,VA,VB

Vector Compare Greater-Than Unsigned Halfword [Record] (AltiVec specific)

vcmpgtuh.

VT,VA,VB

vcmpgtuw

VT,VA,VB

Vector Compare Greater-Than Unsigned Word [Record] (AltiVec specific)

vcmpgtuw.

VT,VA,VB

vctsxs

VT,VB,UIM

Vector Convert To Signed fiXed-point word Saturate (AltiVec specific)

vctuxs

VT,VB,UIM

Vector Convert To Unsigned fiXed-point word Saturate (AltiVec specific)

vexptefp

VT,VB

Vector 2 Raised to the Exponent Estimate Float (AltiVec specific)

vlogefp

VT,VB

Vector Log 2 Estimate Float (AltiVec specific)

vmaxfp

VT,VA,VB

Vector Maximum Float (AltiVec specific)

vmaxsb

VT,VA,VB

Vector Maximum Signed Byte (AltiVec specific)

vmaxsh

VT,VA,VB

Vector Maximum Signed Halfword (AltiVec specific)

vmaxsw

VT,VA,VB

Vector Maximum Signed Word (AltiVec specific)

vmaxub

VT,VA,VB

Vector Maximum Unsigned Byte (AltiVec specific)

vmaxuh

VT,VA,VB

Vector Maximum Unsigned Halfword (AltiVec specific)

vmaxuw

VT,VA,VB

Vector Maximum Unsigned Word (AltiVec specific)

vmhaddshs

VT,VA,VB,VC

Vector Multiply-High and Add Signed Halfword Saturate (AltiVec specific)

vmhraddshs

VT,VA,VB,VC

Vector Multiply-High Round and Add Signed Halfword Saturate (AltiVec specific)

vminfp

VT,VA,VB

Vector Minimum Float (AltiVec specific)

vminsb

VT,VA,VB

Vector Minimum Signed Byte (AltiVec specific)

vminsh

VT,VA,VB

Vector Minimum Signed Halfword (AltiVec specific)

vminsw

VT,VA,VB

Vector Minimum Signed Word (AltiVec specific)

vminub

VT,VA,VB

Vector Minimum Unsigned Byte (AltiVec specific)

vminuh

VT,VA,VB

Vector Minimum Unsigned Halfword (AltiVec specific)

vminuw

VT,VA,VB

Vector Minimum Unsigned Word (AltiVec specific)

vmladduhm

VT,VA,VB,VC

Vector Multiply-Low and Add Unsigned Halfword Modulo (AltiVec specific)

vmr

VT,VS

Vector Move Register (AltiVec specific)

vmrghb

VT,VA,VB

Vector Merge High Byte (AltiVec specific)

vmrghh

VT,VA,VB

Vector Merge High Halfword (AltiVec specific)

vmrghw

VT,VA,VB

Vector Merge High Word (AltiVec specific)

vmrglb

VT,VA,VB

Vector Merge Low Byte (AltiVec specific)

vmrglh

VT,VA,VB

Vector Merge Low Halfword (AltiVec specific)

vmrglw

VT,VA,VB

Vector Merge Low Word (AltiVec specific)

vrsqrtefp

VT,VB

Vector Reciprocal Square Root Estimate Float (AltiVec specific)

vmsummbm

VT,VA,VB,VC

Vector Multiply-Sum Mixed-sign Byte Modulo (AltiVec specific)

vmsumshm

VT,VA,VB,VC

Vector Multiply-Sum Signed Halfword Modulo (AltiVec specific)

vmsumshs

VT,VA,VB,VC

Vector Multiply-Sum Signed Halfword Saturate (AltiVec specific)

vmsumubm

VT,VA,VB,VC

Vector Multiply-Sum Unsigned Byte Modulo (AltiVec specific)

vmsumuhm

VT,VA,VB,VC

Vector Multiply-Sum Unsigned Halfword Modulo (AltiVec specific)

vmsumuhs

VT,VA,VB,VC

Vector Multiply-Sum Unsigned Halfword Saturate (AltiVec specific)

vmulesb

VT,VA,VB

Vector Multiply Even Signed Byte (AltiVec specific)

vmuleub

VT,VA,VB

Vector Multiply Even Unsigned Byte (AltiVec specific)

vmulesh

VT,VA,VB

Vector Multiply Even Signed Halfword (AltiVec specific)

vmuleuh

VT,VA,VB

Vector Multiply Even Unsigned Halfword (AltiVec specific)

vmulosb

VT,VA,VB

Vector Multiply Odd Signed Byte (AltiVec specific)

vmuloub

VT,VA,VB

Vector Multiply Odd Unsigned Byte (AltiVec specific)

vmulosh

VT,VA,VB

Vector Multiply Odd Signed Halfword (AltiVec specific)

vmulouh

VT,VA,VB

Vector Multiply Odd Unsigned Halfword (AltiVec specific)

vnmsubfp

VT,VA,VC,VB

Vector Negative Multiply-Subtract Float (AltiVec specific)

vnor

VT,VA,VB

Vector Logical NOR (AltiVec specific)

vnot

VT,VS

Vector Logical Complement (AltiVec specific)

vor

VT,VA,VB

Vector Logical OR (AltiVec specific)

vperm

VT,VA,VB,VC

Vector Permute (AltiVec specific)

vpkpx

VT,VA,VB

Vector Pack Pixel32 (AltiVec specific)

vpkshss

VT,VA,VB

Vector Pack Signed Halfword Signed Saturate (AltiVec specific)

vpkshus

VT,VA,VB

Vector Pack Signed Halfword Unsigned Saturate (AltiVec specific)

vpkswss

VT,VA,VB

Vector Pack Signed Word Signed Saturate (AltiVec specific)

vpkswus

VT,VA,VB

Vector Pack Signed Word Unsigned Saturate (AltiVec specific)

vpkuhum

VT,VA,VB

Vector Pack Unsigned Halfword Unsigned Modulo (AltiVec specific)

vpkuhus

VT,VA,VB

Vector Pack Unsigned Halfword Unsigned Saturate (AltiVec specific)

vpkuwum

VT,VA,VB

Vector Pack Unsigned Word Unsigned Modulo (AltiVec specific)

vpkuwus

VT,VA,VB

Vector Pack Unsigned Word Unsigned Saturate (AltiVec specific)

vrefp

VT,VB

Vector Reciprocal Estimate Float (AltiVec specific)

vrfim

VT,VB

Vector Round to Floating-Point Integer toward Minus infinity (AltiVec specific)

vrfin

VT,VB

Vector Round to Floating-Point Integer Nearest (AltiVec specific)

vrfip

VT,VB

Vector Round to Floating-Point Integer toward Positive infinity (AltiVec specific)

vrfiz

VT,VB

Vector Round to Floating-Point Integer toward Zero (AltiVec specific)

vrlb

VT,VA,VB

Vector Rotate Left Integer Byte (AltiVec specific)

vrlh

VT,VA,VB

Vector Rotate Left Integer Halfword (AltiVec specific)

vrlw

VT,VA,VB

Vector Rotate Left Integer Word (AltiVec specific)

vsel

VT,VA,VB,VC

Vector Conditional Select (AltiVec specific)

vsl

VT,VA,VB

Vector Shift Left (AltiVec specific)

vslb

VT,VA,VB

Vector Shift Left Integer Byte (AltiVec specific)

vsldoi

VT,VA,VB,SH

Vector Shift Left Double by Octet Immediate (AltiVec specific)

vslh

VT,VA,VB

Vector Shift Left Integer Halfword (AltiVec specific)

vslo

VT,VA,VB

Vector Shift Left by Octet (AltiVec specific)

vslw

VT,VA,VB

Vector Shift Left Integer Word (AltiVec specific)

vspltb

VT,VB,UIM

Vector Splat Byte (AltiVec specific)

vsplth

VT,VB,UIM

Vector Splat Halfword (AltiVec specific)

vspltisb

VT,SIM

Vector Splat Immediate Signed Byte (AltiVec specific)

vspltish

VT,SIM

Vector Splat Immediate Signed Halfword (AltiVec specific)

vspltisw

VT,SIM

Vector Splat Immediate Signed Word (AltiVec specific)

vspltw

VT,VB,UIM

Vector Splat Word (AltiVec specific)

vsr

VT,VA,VB

Vector Shift Right (AltiVec specific)

vsrab

VT,VA,VB

Vector Shift Right Algebraic Byte (AltiVec specific)

vsrah

VT,VA,VB

Vector Shift Right Algebraic Halfword (AltiVec specific)

vsraw

VT,VA,VB

Vector Shift Right Algebraic Word (AltiVec specific)

vsrb

VT,VA,VB

Vector Shift Right Byte (AltiVec specific)

vsrh

VT,VA,VB

Vector Shift Right Halfword (AltiVec specific)

vsro

VT,VA,VB

Vector Shift Right by Octet (AltiVec specific)

vsrw

VT,VA,VB

Vector Shift Right Word (AltiVec specific)

vsubcuw

VT,VA,VB

Vector Subtract & write Carry-out Unsigned Word (AltiVec specific)

vsubfp

VT,VA,VB

Vector Subtract Float (AltiVec specific)

vsubsbs

VT,VA,VB

Vector Subtract Signed Byte Saturate (AltiVec specific)

vsubshs

VT,VA,VB

Vector Subtract Signed Halfword Saturate (AltiVec specific)

vsubsws

VT,VA,VB

Vector Subtract Signed Word Saturate (AltiVec specific)

vsububm

VT,VA,VB

Vector Subtract Unsigned Byte Modulo (AltiVec specific)

vsububs

VT,VA,VB

Vector Subtract Unsigned Byte Saturate (AltiVec specific)

vsubuhm

VT,VA,VB

Vector Subtract Unsigned Halfword Modulo (AltiVec specific)

vsubuhs

VT,VA,VB

Vector Subtract Unsigned Halfword Saturate (AltiVec specific)

vsubuwm

VT,VA,VB

Vector Subtract Unsigned Word Modulo (AltiVec specific)

vsubuws

VT,VA,VB

Vector Subtract Unsigned Word Saturate (AltiVec specific)

vsumsws

VT,VA,VB

Vector Sum Across Signed Word Saturate (AltiVec specific)

vsum2sws

VT,VA,VB

Vector Sum Across Partial (1/2) Signed Word Saturate (AltiVec specific)

vsum4sbs

VT,VA,VB

Vector Sum Across Partial (1/4) Signed Byte Saturate (AltiVec specific)

vsum4shs

VT,VA,VB

Vector Sum Across Partial (1/4) Signed Halfword Saturate (AltiVec specific)

vsum4ubs

VT,VA,VB

Vector Sum Across Partial (1/4) Unsigned Byte Saturate (AltiVec specific)

vupkhpx

VT,VB

Vector Unpack High Pixel16 (AltiVec specific)

vupkhsb

VT,VB

Vector Unpack High Signed Byte (AltiVec specific)

vupkhsh

VT,VB

Vector Unpack High Signed Halfword (AltiVec specific)

vupklsb

VT,VB

Vector Unpack Low Signed Byte (AltiVec specific)

vupklpx

VT,VB

Vector Unpack Low Pixel16 (AltiVec specific)

vupklsh

VT,VB

Vector Unpack Low Signed Halfword (AltiVec specific)

vxor

VT,VA,VB

Vector Logical XOR (AltiVec specific)

X

Operator

Operands

Operation Name

xor

RA,RT,RB

XOR

xor.

RA,RT,RB

xori

RA,RT,UI

XOR Immediate

xoris

RA,RT,UI

XOR Immediate Shifted