<!--
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  "framework" : "Hypervisor",
  "identifier" : "/documentation/Hypervisor/1469645-vmx-capabilities",
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  "role" : "collectionGroup",
  "title" : "VMX Capabilities"
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# VMX Capabilities

An enumeration that represents the available VMX capabilities.

## Discussion

The capabilites available to the hypervisor can vary depending on the specific hardware platform or OS release. Use the [`hv_vmx_read_capability(_:_:)`](/documentation/Hypervisor/hv_vmx_read_capability(_:_:)) API at run time to determine the capabilities that can you can select.

The example below demonstrates the process for checking for the availability a specific capability, here checking for the avaiability of timestamp-counter scaling (TSC scaling):

```objc
static uint64_t canonicalize(uint64_t ctrl, uint64_t mask) {
    return (ctrl | (mask & 0xffffffff)) & (mask >> 32);
}

main() {
    
    // Fetch the supported capabilities for the PROCBASED2 field
    if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &proc2_cap) != 0)
        errx(1, "vcpu_read_capability(%u, CAP_VMX_PROCBASED2) failed", vcpu);
    
    // Apply the constraints to our request to use TSC scaling
    const uint64_t newcap = canonicalize(CPU_BASED2_TSC_SCALING, proc2_cap);
    
    // Test to see if that bit is supported on this platform
    if ((newcap & CPU_BASED2_TSC_SCALING) == 0) {
        warnx(“TSC scaling not supported on this platform”);
    }
    
    // Continue, but without TSC scaling ...
    write_vmcs(vcpu, VMCS_CTRL_CPU_BASED2, newcap);

    // ...
}
```

## Topics

### Capabilities

[`PIN_BASED_INTR`](/documentation/Hypervisor/PIN_BASED_INTR)

The value that controls whether external interrupts cause VM exits.

[`PIN_BASED_NMI`](/documentation/Hypervisor/PIN_BASED_NMI)

The value that controls whether external non-maskable interrupts cause VM exits.

[`PIN_BASED_VIRTUAL_NMI`](/documentation/Hypervisor/PIN_BASED_VIRTUAL_NMI)

The value that controls blocking of non-maskable interrupts.

[`PIN_BASED_PREEMPTION_TIMER`](/documentation/Hypervisor/PIN_BASED_PREEMPTION_TIMER)

The value that controls whether the VMX-preemption timer counts down in VMX non-root operation.

[`PIN_BASED_POSTED_INTR`](/documentation/Hypervisor/PIN_BASED_POSTED_INTR)

The value that controls whether the processor gives special treatment to interrupts with posted-interrupt notification vectors.

[`CPU_BASED_IRQ_WND`](/documentation/Hypervisor/CPU_BASED_IRQ_WND)

The value that controls whether a VM exits at the beginning of any instruction where there’s no blocking of interrupts and the interrupt flag is 1.

[`CPU_BASED_TSC_OFFSET`](/documentation/Hypervisor/CPU_BASED_TSC_OFFSET)

The value that controls whether reading the timestamp-counter MSRs changes depending on the value of the timestamp-counter offset field.

[`CPU_BASED_HLT`](/documentation/Hypervisor/CPU_BASED_HLT)

The value that controls whether the execution of HALT instructions cause VM exits.

[`CPU_BASED_INVLPG`](/documentation/Hypervisor/CPU_BASED_INVLPG)

The value that controls whether the execution of invalid page instructions (INVLPG) cause VM exits.

[`CPU_BASED_MWAIT`](/documentation/Hypervisor/CPU_BASED_MWAIT)

The value that controls whether the execution of Monitor Wait instructions (MWAIT) cause VM exits.

[`CPU_BASED_RDPMC`](/documentation/Hypervisor/CPU_BASED_RDPMC)

The value that controls whether the execution of Read Performance Monitoring Counters instructions (RDPMC) cause VM exits.

[`CPU_BASED_RDTSC`](/documentation/Hypervisor/CPU_BASED_RDTSC)

The value that controls whether the execution of Read Timestamp-Counter instructions (RDTSC) cause VM exits.

[`CPU_BASED_CR3_LOAD`](/documentation/Hypervisor/CPU_BASED_CR3_LOAD)

The value that controls whether executions of MOV to Control Register 3 (CR3) cause VM exits.

[`CPU_BASED_CR3_STORE`](/documentation/Hypervisor/CPU_BASED_CR3_STORE)

The value that controls whether executions of MOV from Control Register 3 (CR3) cause VM exits.

[`CPU_BASED_CR8_LOAD`](/documentation/Hypervisor/CPU_BASED_CR8_LOAD)

The value that controls whether executions of MOV to Control Register 8 (CR8) cause VM exits.

[`CPU_BASED_CR8_STORE`](/documentation/Hypervisor/CPU_BASED_CR8_STORE)

The value that controls whether executions of MOV from Control Register 8 (CR8) cause VM exits.

[`CPU_BASED_TPR_SHADOW`](/documentation/Hypervisor/CPU_BASED_TPR_SHADOW)

The value that controls enabling Task Priority Register (TPR) virtualization and other APIC-virtualization features.

[`CPU_BASED_VIRTUAL_NMI_WND`](/documentation/Hypervisor/CPU_BASED_VIRTUAL_NMI_WND)

The value that controls if a VM exit occurs at the beginning of any instruction if there’s no virtual-NMI blocking.

[`CPU_BASED_MOV_DR`](/documentation/Hypervisor/CPU_BASED_MOV_DR)

The value that controls whether executions of MOV to or from Debug Registers (DR) cause VM exits.

[`CPU_BASED_UNCOND_IO`](/documentation/Hypervisor/CPU_BASED_UNCOND_IO)

The value that controls whether executions of various I/O instructions cause VM exits.

[`CPU_BASED_IO_BITMAPS`](/documentation/Hypervisor/CPU_BASED_IO_BITMAPS)

The value that controls whether to use I/O bitmaps to restrict executions of I/O instructions.

[`CPU_BASED_MTF`](/documentation/Hypervisor/CPU_BASED_MTF)

The value that controls enabling the monitor trap flag debugging feature.

[`CPU_BASED_MSR_BITMAPS`](/documentation/Hypervisor/CPU_BASED_MSR_BITMAPS)

The value that controls use of whether Model Specific Register (MSR) bitmaps to control execution of the read-from and write-to MSR instructions.

[`CPU_BASED_MONITOR`](/documentation/Hypervisor/CPU_BASED_MONITOR)

The value that controls whether executions of the Set Up Monitor Address instruction (MONITOR) cause VM exits.

[`CPU_BASED_PAUSE`](/documentation/Hypervisor/CPU_BASED_PAUSE)

The value that controls whether executions of spin-wait loop (PAUSE) instruction causes VM exits.

[`CPU_BASED_SECONDARY_CTLS`](/documentation/Hypervisor/CPU_BASED_SECONDARY_CTLS)

The value that conntrols use of the secondary processor-based VM-execution controls.

[`CPU_BASED2_VIRTUAL_APIC`](/documentation/Hypervisor/CPU_BASED2_VIRTUAL_APIC)

The value that controls whether the logical processor provides special treatment for access to the Advanced Programmable Interrupt Controller (APIC).

[`CPU_BASED2_EPT`](/documentation/Hypervisor/CPU_BASED2_EPT)

The value that controls enabling extended page tables (EPT).

[`CPU_BASED2_DESC_TABLE`](/documentation/Hypervisor/CPU_BASED2_DESC_TABLE)

The value that controls whether executions of descriptor table instructions cause VM exits.

[`CPU_BASED2_RDTSCP`](/documentation/Hypervisor/CPU_BASED2_RDTSCP)

The value that controls whether any execution of read timestamp-counter and processor ID instruction (RDTSCP) causes an invalid-opcode exception.

[`CPU_BASED2_X2APIC`](/documentation/Hypervisor/CPU_BASED2_X2APIC)

The value that controls the logical processor’s treatment of reading/writing of Model Specific Registers to APIC MSRs.

[`CPU_BASED2_VPID`](/documentation/Hypervisor/CPU_BASED2_VPID)

The value that controls the association of cached translations of linear addresses with a virtual processor identifier (VPID).

[`CPU_BASED2_WBINVD`](/documentation/Hypervisor/CPU_BASED2_WBINVD)

The value that controls whether executions of the Invalidate Cache with Writeback instruction (WBINVD) cause VM exits.

[`CPU_BASED2_UNRESTRICTED`](/documentation/Hypervisor/CPU_BASED2_UNRESTRICTED)

The value that controls whether guest software may run in unpaged protected mode or in real address mode.

[`CPU_BASED2_APIC_REG_VIRT`](/documentation/Hypervisor/CPU_BASED2_APIC_REG_VIRT)

This value controls whether the logical processor virtualizes certain advanced programmable interrupt controller (APIC) accesses.

[`CPU_BASED2_VIRT_INTR_DELIVERY`](/documentation/Hypervisor/CPU_BASED2_VIRT_INTR_DELIVERY)

The value that enables evaluation and delivery of pending virtual interrupts and emulation of writes to the APIC registers that control interrupt prioritization.

[`CPU_BASED2_PAUSE_LOOP`](/documentation/Hypervisor/CPU_BASED2_PAUSE_LOOP)

The value that controls whether a series of executions of the PAUSE instruction can cause a VM exit.

[`CPU_BASED2_RDRAND`](/documentation/Hypervisor/CPU_BASED2_RDRAND)

The value that controls whether executions of the hardware random number generator instruction (RDRAND) cause VM exits.

[`CPU_BASED2_INVPCID`](/documentation/Hypervisor/CPU_BASED2_INVPCID)

The value that controls whether any execution of the Invalidate Process-Context Identifier instruction (INVPCID) causes an invalid opcode exception.

[`CPU_BASED2_VMFUNC`](/documentation/Hypervisor/CPU_BASED2_VMFUNC)

The value that enables use of the “Invoke VM function” (VMFUNC) instruction in VMX non-root operation.

[`CPU_BASED2_VMCS_SHADOW`](/documentation/Hypervisor/CPU_BASED2_VMCS_SHADOW)

The value that controls whether execution of VMREAD and VMWRITE in VMX non-root operation may access a shadow VMCS instead of causing a VM exit.

[`CPU_BASED2_ENCLS_EXIT_MAP`](/documentation/Hypervisor/CPU_BASED2_ENCLS_EXIT_MAP)

The value that controls whether executions of Enclave Instruction Leaf Functions (ENCLS) cause examination of the ENCLS-exiting bitmap to determine whether the instruction causes a VM exit.

[`CPU_BASED2_RDSEED`](/documentation/Hypervisor/CPU_BASED2_RDSEED)

The value that controls whether executions of random number generator instructions (RDSEED) cause VM exits.

[`CPU_BASED2_PML`](/documentation/Hypervisor/CPU_BASED2_PML)

The value that controls whether an access to a guest-physical address that sets an extended page table (EPT) dirty bit also adds an entry to the page-modification log.

[`CPU_BASED2_EPT_VE`](/documentation/Hypervisor/CPU_BASED2_EPT_VE)

The value that controls whether extended page table (EPT) violations cause virtualization exceptions instead of VM exits.

[`CPU_BASED2_PT_CONCEAL_VMX`](/documentation/Hypervisor/CPU_BASED2_PT_CONCEAL_VMX)

The value that controls whether the processor trace facility suppresses information that the processor was in VMX non-root operation.

[`CPU_BASED2_XSAVES_XRSTORS`](/documentation/Hypervisor/CPU_BASED2_XSAVES_XRSTORS)

The value that controls whether any execution of save or restore state instructions (XSAVES or XRSTORS) causes an invalid opcode exception.

[`CPU_BASED2_EPT_MODE_BASED_EXEC`](/documentation/Hypervisor/CPU_BASED2_EPT_MODE_BASED_EXEC)

The value that controls whether to base extended page table (EPT) execute permissions on whether access to a linear address is supervisor or user mode.

[`CPU_BASED2_EPT_SUBPAGE_WRITE`](/documentation/Hypervisor/CPU_BASED2_EPT_SUBPAGE_WRITE)

The value that controls whether extended page table (EPT) write permissions specify granularity of 128 bytes.

[`CPU_BASED2_PT_GUEST_PHYSICAL`](/documentation/Hypervisor/CPU_BASED2_PT_GUEST_PHYSICAL)

The value that controls whether to treat all output addresses used by Intel Processor Trace as guest-physical addresses and translated using the extended page table.

[`CPU_BASED2_TSC_SCALING`](/documentation/Hypervisor/CPU_BASED2_TSC_SCALING)

The value that controls whether the execution of various read time stamp counters and read model-specific registers that read from the IA32 timestamp counter model specific register return a value modified by the TSC multiplier field.

[`CPU_BASED2_USER_WAIT_PAUSE`](/documentation/Hypervisor/CPU_BASED2_USER_WAIT_PAUSE)

The value that controls whether any execution of TPAUSE, UMONITOR, or UMWAIT instrucitons generate an illegal opcode exception.

[`CPU_BASED2_ENCLV_EXIT_MAP`](/documentation/Hypervisor/CPU_BASED2_ENCLV_EXIT_MAP)

The value that controls whether executions of an enclave VMM function instruction (ENCLV) checks the ENCLV-exiting bitmap to determine whether the instruction causes a VM exit.

[`VMX_EPT_VPID_SUPPORT_AD`](/documentation/Hypervisor/VMX_EPT_VPID_SUPPORT_AD)

The value that controls if extended page tables (EPT) support accessed and dirty flags.

[`VMX_EPT_VPID_SUPPORT_EXONLY`](/documentation/Hypervisor/VMX_EPT_VPID_SUPPORT_EXONLY)

The value that controls whether extended page tables (EPT) support execute-only translations.

[`VMEXIT_SAVE_DBG_CONTROLS`](/documentation/Hypervisor/VMEXIT_SAVE_DBG_CONTROLS)

Thievalue that controls whether to save debug register 7 DR7 and the IA32 debug control DEBUGCTL MSR on VM exit.

[`VMEXIT_HOST_IA32E`](/documentation/Hypervisor/VMEXIT_HOST_IA32E)

This value controls, on processors that support Intel 64 architecture, whether a logical processor is in 64-bit mode after the next VM exit.

[`VMEXIT_LOAD_IA32_PERF_GLOBAL_CTRL`](/documentation/Hypervisor/VMEXIT_LOAD_IA32_PERF_GLOBAL_CTRL)

The value that controls whether to load the IA32_PERF_GLOBAL_CTRL model specific register on VM exit.

[`VMEXIT_ACK_INTR`](/documentation/Hypervisor/VMEXIT_ACK_INTR)

The value that controls whether the logical processor sends an acknowledgement to the interrupt controller when the VM exits.

[`VMEXIT_SAVE_IA32_PAT`](/documentation/Hypervisor/VMEXIT_SAVE_IA32_PAT)

The value that controls whether to save the IA32_EFER model specific register on VM exit.

[`VMEXIT_LOAD_IA32_PAT`](/documentation/Hypervisor/VMEXIT_LOAD_IA32_PAT)

The value that controls whether to load the IA32_EFER mode specific register on VM exit.

[`VMEXIT_SAVE_EFER`](/documentation/Hypervisor/VMEXIT_SAVE_EFER)

The value that controls whether to save the IA32_EFER MSR on VM exit.

[`VMEXIT_LOAD_EFER`](/documentation/Hypervisor/VMEXIT_LOAD_EFER)

The value that controls whether to load the IA32_EFER MSR on VM exit.

[`VMEXIT_SAVE_VMX_TIMER`](/documentation/Hypervisor/VMEXIT_SAVE_VMX_TIMER)

The value that controls whether to save the value of the VMX-preemption timer on VM exit.

[`VMEXIT_CLEAR_IA32_BNDCFGS`](/documentation/Hypervisor/VMEXIT_CLEAR_IA32_BNDCFGS)

The value that controls whether to clear the IA32_BNDCFGS model specific register on VM exit.

[`VMEXIT_PT_CONCEAL_VMX`](/documentation/Hypervisor/VMEXIT_PT_CONCEAL_VMX)

The value that controls whether the Intel Processor Trace produces a paging information packet on VM exit or a VMCS packet on SMM VM exit.

[`VMEXIT_CLEAR_IA32_RTIT_CTL`](/documentation/Hypervisor/VMEXIT_CLEAR_IA32_RTIT_CTL)

The value that controls whether to clear the IA32_RTIT_CTL model specific register (MSR) on VM exit.

[`VMEXIT_LOAD_CET_STATE`](/documentation/Hypervisor/VMEXIT_LOAD_CET_STATE)

The value that controls whether to load CET-related MSRs and SPP on VM exit.

[`VMENTRY_LOAD_DBG_CONTROLS`](/documentation/Hypervisor/VMENTRY_LOAD_DBG_CONTROLS)

The value that controls whetherto load Debug Register 7 and the IA32_DEBUGCTL model specific register (MSR) on VM entry.

[`VMENTRY_GUEST_IA32E`](/documentation/Hypervisor/VMENTRY_GUEST_IA32E)

The value that controls whether the logical processor is in IA-32e mode after VM entry.

[`VMENTRY_SMM`](/documentation/Hypervisor/VMENTRY_SMM)

The value that controls whether the logical processor is in system-management mode (SMM) after VM entry.

[`VMENTRY_DEACTIVATE_DUAL_MONITOR`](/documentation/Hypervisor/VMENTRY_DEACTIVATE_DUAL_MONITOR)

The value that controls whether the treatment of SMIs and system-management mode (SMM) is in effect after the VM entry.

[`VMENTRY_LOAD_IA32_PERF_GLOBAL_CTRL`](/documentation/Hypervisor/VMENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)

The value that controls whether to load the IA32_PERF_GLOBAL_CTRL model specific register on VM entry.

[`VMENTRY_LOAD_IA32_PAT`](/documentation/Hypervisor/VMENTRY_LOAD_IA32_PAT)

The value that controls whether to load the IA32_PAT model specific register on VM entry.

[`VMENTRY_LOAD_EFER`](/documentation/Hypervisor/VMENTRY_LOAD_EFER)

The value that determines whether to load the IA32_EFER model specific register on VM entry.

[`VMENTRY_LOAD_IA32_BNDCFGS`](/documentation/Hypervisor/VMENTRY_LOAD_IA32_BNDCFGS)

The value that controls whether to load the IA32_BNDCFGS model specific register on VM entry.

[`VMENTRY_PT_CONCEAL_VMX`](/documentation/Hypervisor/VMENTRY_PT_CONCEAL_VMX)

The value that controls whether the Intel Processor Trace produces a paging information packet (PIP) on a VM entry or a VMCS packet on a VM entry that returns from system-management mode.

[`VMENTRY_LOAD_IA32_RTIT_CTL`](/documentation/Hypervisor/VMENTRY_LOAD_IA32_RTIT_CTL)

The value that controls whether to clear the IA32_RTIT_CTL model specific register (MSR) on VM exit.

[`VMENTRY_LOAD_CET_STATE`](/documentation/Hypervisor/VMENTRY_LOAD_CET_STATE)

The value that controls whether to load CET-related model specific registers and SPP on VM exit.


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