Processor Bus

The processor bus is a 600 MHz bus connecting the processor to the U3L IC. The bus has 32-bit wide data running in both directions. The processor has 42-bit wide addresses.

The single processor Power Mac G5 system controller is built with 130-nanometer SOI technology. This point-to-point architecture provides each subsystem with dedicated bandwidth to main memory. The U3L I/O implements an independent processor interface. The processor clock rate is either 900 MHz or 1.8 GHz (see Power Management). The processor clock is derived from a PLL which multiplies the reference clock by preset intervals of 12 times.

Out-of-order completion allows the memory controller to optimize the data bus efficiency by transferring whichever data is ready, rather than having to pass data across the bus in the order the transactions were posted on the bus. This means that a fast DDR SDRAM read can pass a slow PCI read, potentially enabling the processor to do more before it has to wait on the PCI data.

Main Memory Bus

The single processor Power Mac G5 main memory bus connects the main memory to the U3L IC via the 128-bit data bus. The memory modules are 400 MHz (PC3200) DDR SDRAM DIMMs. Maximum system memory is 4 GB.

Standard supported DIMM sizes are 128, 256, 512 MB, and 1 GB. The DIMMs must be unbuffered and installed in pairs of the same size.

For more information about memory DIMMs and installation, see RAM Expansion.

Accelerated Graphics Port Bus

The accelerated graphics port (AGP 8x Pro) bus is a 266/533 MHz, 32-bit bus connecting the AGP card to the U3L IC. DDR data is transmitted at both edges of the clock for peak transfers of 2.1 GBps.

The AGP bus is an enhanced PCI bus with extra functionality to burst texture data and other graphics across the port up to 8 times faster than a 66 MHz PCI port. The single processor Power Mac G5 computer’s AGP implementation is compatible with version 3 of the AGP specification and with the Pro version of AGP. AGP 3.0 enables deeply pipelined memory read and write operations and demultiplexing of address and data on the bus.

To further improve the performance of the AGP bus, the U3L IC supports a graphics address remapping table (GART). Because the virtual memory system organizes main memory as randomly distributed 4 KB pages, DMA transactions for more than 4 KB of data must perform scatter-gather operations. To avoid this necessity for AGP transactions, the GART is used by the AGP bridge in the U3L to translate a linear address space for AGP transactions into physical addresses in main memory.

The U3L IC also supports a DMA Address Relocation Table (DART) that provides the same functions for AGP as does the GART, except that the functions are for devices attached to HyperTransport. Most device drivers do not require special knowledge of the DART because IOKit will configure it automatically if the driver uses IOMemoryDescriptors.

For more information on the graphics cards installed in the AGP slot, refer to Graphics Cards.

Internal PCI Bus

An internal 33 MHz PCI bus connects the Shasta I/O controller to the boot ROM, the AirPort Extreme Card slot, and the USB controller. The U3L IC used in the single processor Power Mac G5 supports the PCI write combining feature. This feature allows sequential write transactions involving the Memory Write or Memory Write and Invalidate commands to be combined into a single PCI transaction. For memory write transactions to be combined, they must be sequential, ascending, and non-overlapping PCI addresses. Placing an eieio or sync command between the write commands prevents any write combining.

PCI Expansion Slots

The single processor Power Mac G5 computer provides three 64-bit 33 MHz PCI slots that interface to the Shasta I/O.

Each slot has room for a full size 12.335-inch or short 6.926-inch card. The slots are numbered from 2 to 4 on back panel, on the PCB, and in the Apple System Profiler. Slot one is the AGP. A total of 90 W is allocated to the three PCI slots and the AGP slot.

The connectors to the PCI slots are 3.3 V keyed and support 32-bit and 64-bit buses. The connectors include a PME signal which allows a PCI card to wake the computer from sleep.

The slots (12.335 inch) have a capture feature which is at the end of the slot. If a card exceeds the short length it is recommended that the long length be used rather than an intermediate length, to assure the card stays secure if and when the system is in shipment.

For more information, refer to PCI Expansion Slots.

DMA Support

The Shasta ICs provide DB-DMA (descriptor-based direct memory access) support for the following I/O channels:

• Ultra ATA/100

• Ethernet interface

• FireWire interface

• I2S channel to the sound subsystem

• Serial ATA

The DB-DMA system provides a scatter-gather process based on memory-resident data structures that describe the data transfers. The DMA engine is enhanced to allow bursting of data files for improved performance.

Wireless LAN Module

The optional AirPort Extreme wireless LAN module connects via the PCI interface.

The AirPort Extreme Card wireless LAN module contains a media access controller (MAC), a digital signal processor (DSP), and a radio-frequency (RF) section. The module has an antenna port on the rear of the computer.

The AirPort Extreme Card is based on the IEEE 802.11g standard. The card transmits and receives data at up to 54 Mbps and is compatible with Apple AirPort systems as well as other 802.11b and 802.11g Wi-Fi certified products. For information about its operation, see AirPort Extreme Card.

The build-to-order Bluetooth connectivity comes off the USB controller. See Bluetooth Technology for more information.

Modem Slot Support

The Shasta IC supports the modem and provides DB-DMA (descriptor-based direct memory access) support for the modem slot interface. The modem is connected via an I2S interface.

The internal hardware modem is a separate module that contains a modem controller IC, a data pump, and the interface to the telephone line (DAA). For more information about the modem, see Internal Modem.

Boot ROM

The boot ROM consists of 1 MB of on-board flash EEPROM. The boot ROM includes the hardware-specific code and tables needed to start up the computer using Open Firmware, to load an operating system, and to provide common hardware access services.

Ethernet Controller

The Vesta IC provides the Ethernet functions and includes an Ethernet media access controller (MAC) and PHY.

The MAC implements the link layer. It is connected to a PHY via Vesta and provides 10Base-T/UTP, 100Base-TX, or 1000Base-TX operation over a standard twisted-pair interface. The Ethernet port is auto-sensing and self-configuring to allow use of either a cross-over or straight-through cable. The operating speed of the link is automatically negotiated by the PHY and the bridge, router, hub, switch, or other Mac or PC to which the Ethernet port is connected.

For information about the Ethernet port, see Ethernet Port.

FireWire Controllers

The Shasta IC provides the FireWire functions and includes a FireWire controller that supports both IEEE 1394b (FireWire 800) with a maximum data rate of 800 Mbps (100 MBps) and IEEE 1394a (FireWire 400) with a maximum data rate of 400 Mbps (50 MBps). The IC is backwards-compatible with 1394a (FireWire 400). The Shasta IC provides DMA (direct memory access) support for the FireWire interface.

The controller in the Shasta IC implements the FireWire link layer. Vesta is a PHY that implements the electrical signaling protocol of the FireWire interface and provides the electrical signals to the ports.

For more information, see FireWire Ports.

Interrupt Support

The interrupt controller for the single processor Power Mac G5 system is an MPIC cell in the Shasta IC. In addition to accepting internal interrupt sources from the I/O, the MPIC controller accepts internal interrupts from U3L and dedicated interrupt pins.

Serial ATA Interface

Based on the Serial ATA 1.0 specification, Serial ATA (SATA) is a disk-interface technology that delivers up to 1.5 Gbps of performance to each independent drive bus on the single processor Power Mac G5. It provides a scalable, point-to-point connection that allows multiple ports to be aggregated into a single controller. Serial ATA uses a thin, point-to-point cable connection that enables easy routing within a system, avoiding master/slave, daisy-chaining, and termination issues and enabling better airflow within a system.

The Shasta IC implements two Serial ATA revision one ports, each of which accommodates one independent internal hard drive.

For information about the drive bays, see Hard Disk Drives.

Ultra DMA ATA/100 Interface

In the single processor Power Mac G5 computer, the Shasta IC provides an Ultra DMA ATA/100 interface to support the optical drive. For information about specific drives, see Disk Drives.

Sound System Overview

The sound circuitry is connected to the Shasta IC by two standard I2S (inter-IC sound) buses. The Shasta IC provides DB-DMA (descriptor-based direct memory access) support for the I2S port.

The single processor Power Mac G5 circuitry consists of two main components: an analog audio CODEC IC (CODEC) and a S/PDIF receiver IC. The analog audio CODEC IC includes an A/D converter, a D/A converter, and a S/PDIF (Sony/Phillips Digital Interface) digital audio transmitter. The S/PDIF receiver IC includes an S/PDIF digital audio receiver, and a phase-locked loop (PLL).

The CODEC and the S/PDIF receiver connect to Shasta with separate I2S busses (I2Sa and I2Sc). This allows the system to record from the S/PDIF digital audio input while simultaneously recording audio from the analog line input and playing audio over the audio outputs.

Stereo signals from the audio input jack are routed to an analog line input buffer that drives the internal A/D converter in the CODEC. The output of the A/D converter is routed to the Shasta IC over the I2Sa bus.

Digital audio data from the Shasta IC is routed to the D/A converter on the analog CODEC over the I2Sa bus. The analog audio output from the D/A is routed to separate amplifiers that drive the line output, headphone output, and internal speaker.

Digital audio data from the S/PDIF receiver is routed to the Shasta IC over the I2Sc bus. The S/PDIF input always operates in a synchronous mode. The PLL in the digital audio CODEC locks on to the incoming S/PDIF data rate and drives the audio system clocks associated with the I2Sc bus in the single processor Power Mac G5, allowing bit-accurate data processing of the S/PDIF input data. There are two clock modes for the CODEC on the I2Sa bus: internal clock mode and external clock mode. In internal clock mode, the single processor Power Mac G5 is the audio clock master. In this mode, the output sample rate and A/D converter sample rate are controlled by system software; sample rates are selected with the Audio MIDI Setup utility. When in internal clock mode, the S/PDIF input sample rate is asynchronous to the output sample rate of the CODEC. During recording of the S/PDIF input, the S/PDIF input data is processed in a bit-accurate manner. For playback of S/PDIF input data in internal clock mode, audio data from the S/PDIF receiver is converted to the selected output sample rate by a Sample Rate Converter (SRC) implemented in system software. The SRC algorithm will introduce minor audio artifacts in the playthrough of the S/PDIF input stream.In external clock mode, the output sample rate and the A/D sample rate of the Power Mac G5 rate are locked to the sample rate of the S/PDIF input stream. In this mode, the input and output sample rates are synchronous and no SRC is required during playthrough of the S/PDIF input stream.The speaker output is mutually exclusive from the line out, headphones out and S/PDIF outputs. If the speaker output is selected, the line output, the headphones output, and the S/PDIF output are disabled. If any of the line output, the headphones output, or the S/PDIF output are selected, the speaker output is disabled.

For more detail on the audio, see Audio.