Inside Macintosh: PowerPC Numerics / Part 3 - Numerics in PowerPC Assembly Language

Chapter 11 - Introduction to Assembly-Language Numerics

PowerPC Floating-Point Architecture

This section describes those pieces of the PowerPC architecture used in floating-point operations, which include

• floating-point data formats
• floating-point registers
• floating-point special-purpose registers
• the Machine State Register

Floating-Point Data Formats

The PowerPC architecture supports only the single and double floating-point data formats. These formats can represent normalized numbers, denormalized numbers, zeros, NaNs, and Infinities, and are interpreted exactly as described in Chapter 2, "Floating-Point Data Formats." The double-double data format is implemented in software and therefore is not a valid format in PowerPC hardware.

The PowerPC hardware is double-based. This means that when you load a single-format number into a register, it is automatically converted to double format. In addition, all arithmetic operations are performed on double-format numbers unless they are specifically forced to be performed on single-format numbers.

Floating-Point Registers

The PowerPC architecture contains thirty-two 64-bit floating-point registers labeled F0 through F31 (or FP0 through FP31). Because the registers are 64 bits long, they store values using the double data format.

Floating-Point Special-Purpose Registers

The two special-purpose registers that affect floating-point operations are the Floating-Point Status and Control Register and the Condition Register.

The Floating-Point Status and Control Register (FPSCR) is a 32-bit register that stores the current state of the floating-point environment. It specifies the current rounding direction and notes whether any floating-point exceptions are enabled and whether any floating-point exceptions have occurred.

The Condition Register is a 32-bit register that stores the current state of the entire PowerPC processor. It is grouped into eight 4-bit fields labeled CR0 through CR7. Field CR1 reflects the results of floating-point operations. You may also specify one of the Condition Register fields as a place to store the result of a floating-point comparison operation or the result of a floating-point environment manipulation operation.

The FPSCR and the Condition Register are discussed more fully in Chapter 12, "Assembly-Language Environmental Controls."

The Machine State Register

The Machine State Register is a 32-bit supervisor-level register that reflects the current state of the entire PowerPC processor. It differs from the Condition Register in that it is accessible only by supervisor-level software and in that it stores the processor state in a different way. The Machine State Register contains 3 bits that control floating-point computations:

• Bit 18 specifies whether the floating-point instructions are available. If bit 18 is 0, the processor cannot execute floating-point instructions.
• Bits 20 and 23 specify whether floating-point exceptions are enabled. If both of these bits are 0, floating-point instructions will not raise any floating-point exceptions. If either of these bits is set, instructions can raise floating-point exceptions.