Inside Macintosh: PowerPC Numerics / Part 3 - Numerics in PowerPC Assembly Language

Chapter 12 - Assembly-Language Environmental Controls

Inquiries: Class and Sign

As stated in Chapter 2, "Floating-Point Data Formats," the result of a floating-point operation is either a normalized number, a denormalized number, a zero, a NaN, or an Infinity. This section describes how the class and sign of a floating-point number can be determined in PowerPC assembly language.

Floating-Point Result Flags and Condition Codes

FPSCR bits 15 through 19 are the floating-point result flags. Bit 15 is in FPSCR field 3, and bits 16 through 19 are in FPSCR field 4. For many instructions, FPSCR bits 15 through 19 specify the class and sign of the instruction's result. For comparison instructions, bits 16 through 19 store the result of the comparison.

Bit	Meaning
15	The class descriptor. If this bit is set, the result is either a quiet NaN or a denormalized number, depending on the settings of bits 16 through 19.
16	< or < 0. For comparison operations, this bit is set if the first operand is less than the second operand. For other operations, this bit is set if the result is negative (< 0).
17	> or > 0. For comparison operations, this bit is set if the first operand is greater than the second operand. For other operations, this bit is set if the result is positive (> 0).
18	= or = 0. For comparison operations, this bit is set if the first operand is equal to the second operand. For other operations, this bit is set if the result is 0 (= 0).
19	Unordered or NaN. For comparison operations, this bit is set if either of the operands is a NaN. For other operations, this bit is set if the result is a NaN or an Infinity, depending on the value of bit 15.

Table 12-3 shows how bits 15 through 19 are interpreted, depending on whether the previous instruction was a comparison operation or not.

Table 12-3 Values for FPSCR bits 15 through 19

Bits 15-19	Result for comparisons	Result for other operations
00001	Unordered	Not applicable
00010	== (equal to)	+0
00100	> (greater than)	Positive normalized number
00101	Not applicable	+
01000	< (less than)	Negative normalized number
01001	Not applicable	$-$
10001	Unordered	Quiet NaN
10010	== (equal to)	$-0$
10100	> (greater than)	Positive denormalized number
11000	< (less than)	Negative denormalized number

Example: Determining Class

To determine the class of a floating-point operation, copy the FPSCR bits to the Condition Register and then branch on the Condition Register field, as shown in
Listing 12-1. To copy FPSCR bits to the Condition Register, use the mcrfs instruction, which has the form

mcrfs  DST, SRC 

where DST is a 4-bit Condition Register field and SRC is an FPSCR field.

Listing 12-1 Determining the class of an assembler instruction result

   fadd  f0,f1,f2    # sets FPSCR bits 15-19 from f0
   mcrfs 2,3         # copy FPSCR bits 12-15 to CR2
   mcrfs 3,4         # copy FPSCR bits 16-19 to CR3
   # CR bits 11 - 15 are class and sign of f0
   bun   3,inf       # if bit 3 of CR3 is 1, result is 
                     # Infinity or NaN
   beq   3,zero      # if bit 2 of CR3 is 1, result is zero
   blt   3,norm      # if bit 0 or 1 of CR3 is 1, 
   bgt   3,norm      # result is a normalized or 
                     # denormalized number

inf:
   bta   11,NaN      # if bit 11 is set, result = quiet NaN
                     # else result is an Infinity

norm:
   bta   11,denorm   # if bit 11 is set, result is denorm
                     # else result is norm

zero:
   # return class of zero

denorm:
   # return class of denormalized number

The fadd instruction, which adds two floating-point numbers, is one of the many floating-point instructions that set FPSCR bits 15 through 19 to the class and sign of its result. To read these FPSCR bits, Listing 12-1 copies them to the Condition Register using the mcrfs instruction. This instruction operates on 4-bit fields. Bits 15 through 19 are contained in two fields (3 and 4), so two separate mcrfs instructions are required to copy all pertinent bits to the Condition Register. Once the bits are copied, Condition Register fields 2 and 3 contain FPSCR fields 3 and 4, which means that Condition Register bits 11 through 15 reflect FPSCR bits 15 through 19. Next, the branch instructions test the values in the Condition Register and determine what type of result the fadd instruction had.