Inside Macintosh: PowerPC Numerics / Part 3 - Numerics in PowerPC Assembly Language

Chapter 12 - Assembly-Language Environmental Controls

Floating-Point Exceptions

The assembly-language numeric implementation contains the same five floating-point exception flags that are described in the IEEE standard. This section describes how to enable, disable, set, clear, and test these exception flags.

Exception Bits in the FPSCR

Table 12-5 summarizes the FPSCR bits that control floating-point exceptions. For each bit, it shows which FPSCR field contains that bit. Note that all of these bits, unless otherwise specified, are sticky; that is, once set, they stay set until you specifically clear them. For information on exactly what happens when a floating-point exception occurs, see the Motorola PowerPC 601 RISC Microprocessor User's Manual.

Table 12-5 Floating-point exception bits in the FPSCR

Exception	FPSCR field	Bit	Comment
All	0	0	Exception summary; set if any floating-point exception has occurred
	0	1[66]	Exception enable summary; set if any floating-point exception is enabled
Invalid	0	2[66]	Invalid exception summary; bits 7 through 12 or 21 through 23 tell why the exception occurred
	1	7	Signaling NaN
	2	8	$$ +-
	2	9	$$ /
	2	10	$0/0$
	2	11	$0\times$
	3	12	Comparison operation produced invalid
	5	21	Software request produced invalid[67]
	5	22	Square root produced invalid[67]
	5	23	Convert-to-integer operation produced invalid
	6	24	Invalid exception enable/disable
Overflow	0	3	Overflow flag
	6	25	Overflow enable/disable
Underflow	1	4	Underflow flag
	6	26	Underflow enable/disable
Divide-by-zero	1	5	Divide-by-zero flag
	6	27	Divide-by-zero enable/disable
Inexact	1	6	Inexact flag
	3	13[67]	Fraction rounded
	3	14[67]	Fraction inexact
	6	28	Inexact enable/disable

Signaling and Clearing Floating-Point Exceptions

To signal or clear a floating-point exception explicitly, set or clear its bit in the FPSCR. For example, the following instructions signal an overflow exception and then clear that exception:

mtfsb1   3     # sets FPSCR bit 3 to 1, signaling overflow
mtfsb0   3     # clears FPSCR bit 3, so no overflow

These two instructions operate on individual FPSCR bits rather than on 4-bit FPSCR fields. The instruction mtfsb1 sets the specified bit in the FPSCR to 1. The mtfsb1 instruction shown here sets bit 3, which is the overflow exception flag; therefore this instruction signals that an overflow has occurred. Similarly, the mtfsb0 instruction sets the specified FPSCR bit to 0 and therefore clears the overflow exception.

Enabling and Disabling Floating-Point Exceptions

To enable or disable a floating-point exception, set or clear its enable bit in the FPSCR.

Note

Disabling a floating-point exception does not mean that its flag will never be set. For the exact meaning of disabling a particular floating-point exception, see the Motorola PowerPC 601 RISC Microprocessor User's Manual.

For example, the following instructions enable and then disable the overflow exception:

mtfsb1   25    # sets FPSCR bit 25; overflow enabled
mtfsb0   25    # clears FPSCR bit 25; overflow disabled

You can also use the following commands to enable and disable all floating-point exceptions at once:

mtfsfi   6,0      # disables all floating-point exceptions
mtfsfi   6,15     # enables all floating-point exceptions

As you can see from Table 12-1 on page 12-4, FPSCR field 6 contains all of the floating-point exception enable switches, so to enable or disable all floating-point exceptions at once, you need to set or clear this field. The mtfsfi instruction (described on page 12-10) copies a 16-bit signed integer value into an FPSCR field; so the first instruction shown here disables all floating-point exceptions by clearing all bits in
field 6, and the second instruction enables all floating-point exceptions by setting all bits in field 6.

IMPORTANT

For the FPSCR exception enable bits to be valid, bit 20 or 23 of the Machine State Register must be set. For more information, see the Motorola PowerPC 601 RISC Microprocessor User's Manual.

Testing for Floating-Point Exceptions

If you would like to see whether an exception occurred, test the Condition Register. Listing 12-2 checks the Condition Register to see if an exception has occurred and, if so, branches to a routine that determines the type of exception. It uses the fadd. form of the floating-point add instruction to copy the exception summary bits to Condition Register field 1. If the add instruction causes an exception, this example uses the mcrfs instruction (described on page 12-8) to copy the FPSCR fields containing floating-point exception flags to Condition Register fields 2 through 5 and then uses branch instructions to see which type of exception has occurred.

Listing 12-2 Testing for occurrence of floating-point exceptions

   fadd. f0,f1,f2 # f1 + f2 = f0. CR1 contains except.summary
   bta   4,error  # if bit 0 of CR1 is set, go to error
                  # bit 0 is set if any exception occurs
   .              # if clear, continue operation
   .
   .
error:
   mcrfs 2,1   # copy FPSCR bits 4-7 to CR field 2
               # now CR1 and CR2 (bits 6 through 10)
               # contain all exception bits from FPSCR
   bta   6,invalid   # CR bit 6 signals invalid
   bta   7,overflow  # CR bit 7 signals overflow
   bta   8,underflow # CR bit 8 signals underflow
   bta   9,divbyzero # CR bit 9 signals divide-by-zero
   bta   10,inexact  # CR bit 10 signals inexact

invalid:
   mcrfs 2,2   # copy FPSCR bits 8-11 to CR field 2
   mcrfs 3,3   # copy FPSCR bits 12-15 to CR field 3
   mcrfs 4,5   # copy FPSCR bits 20-23 to CR field 4
               # invalid bits are now CR bits 11-16 and bit 23

   # now do exception handling based on which invalid bit
   # is set

overflow:
   # do exception handling for overflow exception

underflow:
   # do exception handling for underflow exception

divbyzero:
   #do exception handling for the divide-by-zero exception

inexact:
   # do exception handling for the inexact exception

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[66] This field is not sticky; it applies only for the last instruction executed.

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[67] Not implemented in MPC601.