Important: The information in this document is obsolete and should not be used for new development.
Comparison Operations
The assembler provides two floating-point comparison instructions:
fcmpo Ordered comparison fcmpu Unordered comparison The only difference is that the ordered comparison instruction generates an invalid exception if one of the input registers contains a NaN.
The comparison instructions have three operands. They are of the form
instr DST
,
SRC1,
SRC2
Comparison instructions are interpreted as
- DST
- A field in the Condition Register (0 through 7) into which the result of the comparison is placed.
- SRC1, SRC2
- Two floating-point registers.
DST \xC6 SRC1 compare SRC2The comparison instructions compare the contents of two floating-point registers and place the results of the comparison in a Condition Register field as well as in bits 16 through 19 (field 4) of the FPSCR. The results in the Condition Register and FPSCR are interpreted as follows:
Result Meaning 0001 Unordered 0010 SRC1 = SRC2 0100 SRC1 > SRC2 1000 SRC1 < SRC2 Use a conditional branch instruction after the comparison instruction to use the results of the comparison, as shown in the following example:
fcmpo 2,f0,f11 # compare f0 to f11 and put result in CR2 blt 2,addr1 # go to addr1 if bit 0 (<) of CR2 is 1 bgt 2,addr2 # go to addr2 if bit 1 (>) of CR2 is 1 beq 2,addr3 # go to addr3 if bit 2 (=) of CR2 is 1 bun 2,addr4 # go to addr4 if bit 3 (unordered) of CR2 is 1