For PMC events of M1, the descriptions for them are vague. For ICACHE_MISS event, the description is 'Instruction cache demand misses', is this counting the numbers of instructions or the numbers of stalled cycles?
I remember these are clearly described for A12. For example, FED_IC_MISS_DEM is describe as 'Counts each cycle where the I-cache makes a demand access that misses', while SYNC_DTLB_MISS is for 'Counts the number of retired load-stores which missed in the DTLB'.
The same question goes for below events of M1, could anyone help to clarify? Thanks!
ICACHE_MISS: Instruction cache demand misses
ITLB_MISS: Instruction TLB misses
DTLB_MISS: Data TLB misses
DCACHE_LOAD_MISS / DCACHE_STORE_MISS: Loads/Stores that miss in the L1 Data Cache
I remember these are clearly described for A12. For example, FED_IC_MISS_DEM is describe as 'Counts each cycle where the I-cache makes a demand access that misses', while SYNC_DTLB_MISS is for 'Counts the number of retired load-stores which missed in the DTLB'.
The same question goes for below events of M1, could anyone help to clarify? Thanks!
ICACHE_MISS: Instruction cache demand misses
ITLB_MISS: Instruction TLB misses
DTLB_MISS: Data TLB misses
DCACHE_LOAD_MISS / DCACHE_STORE_MISS: Loads/Stores that miss in the L1 Data Cache